Optical phase-locked loop for coherent detection optical receiver

A novel subcarrier-based optical phase-locked loop (SC-OPLL/sup /spl reg//), with off-the-shelf optical components, is presented and demonstrated. The method, based on a continuous-wave laser and optical subcarrier modulation using a standard LiNbO/sub 3/ Mach-Zehnder modulator, allows easier practical implementation than the previously proposed OPLL circuits based on laser direct modulation.     

A power-efficient wide-range phase-locked loop

This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations     

A 2-V amplitude-linear phase-locked loop

An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-/spl mu/m CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier, and a voltage-controlled oscillator control buffer is used to define a linear frequency characteristic. The measured performance demonstrates suitability for portable tone-decoding and FM demodulation applications.     

Heterodyne optical phase-locked loop by confocal Fabry-Periotcavity coupled AlGaAs lasers

Two external confocal Fabry-Perot cavity-coupled 0.83-μm AlGaAs lasers phase-locked to one another by a heterodyne optical phase-locked loop are discussed. The phase error under phase-locking conditions was measured using the square root of the Allan variance. The result confirmed that the heterodyne signal was a full replica of the spectrum of the reference RF signal within the loop bandwidth. The estimated phase-error variance was 0.02 rad², i.e. ≃8.1°     

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively     

A high lock-in speed digital phase-locked loop

A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A 2-GHz 1.6-mW phase-locked loop

This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

Some analytical and experimental phase-locked loop results for low signal-to-noise ratios

This paper is concerned with the nonlinear behavior of the second-order phase-locked loop (PLL) in the presence of noise. The loop filter is of the proportional-plus-integral control type. This filter corresponds to the one generally employed for carrier tracking purposes in the implementation of phase-coherent communication systems. The paper is composed essentially of two parts: the first part presents analytical results which pertain to the probability distribution of the phase-error. Since these analytical results are approximations, valid only for certain regions of signal-to-noise ratio, they are complemented by experimental results obtained from simulation of the PLL system in the laboratory. The experimental techniques used to measure the statistical properties of the loop behavior and the corresponding results comprise the second part of the paper. Approximate analytical expressions for the distribution of the system phase-error are first obtained by using the Fokker-Planck apparatus and, secondly, by assuming that the PLL behaves as a very narrow band-pass filter. The range of signal-to-noise ratios for which these approximations are valid is obtained by graphically comparing the analytical expressions to experimentally derived phase-error distributions. In addition, measurements relative to the variance of the phase-error are compared to those predicted by the linear PLL theory and the variance as computed from the approximate solutions. Finally, experimental results relative to the probability distribution of the time intervals between cycle-slipping events are given for signal-to-noise ratios in a range where the linear PLL theory does not apply. In particular, the maximum length of time the loop may be expected to remain in-lock is illustrated graphically as a function of signal-to-noise ratio in the loop bandwidth.     

A 6 GHz 68 mW BiCMOS phase-locked loop

The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 μm, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset     

Very wide range phase-locked loop

A phase-locked loop is described that will capture and lock to any input frequency in the range 1 Hz to 1 MHz without any adjustment. A DC signal proportional to the logarithm of the input frequency is available.     

A low-noise fast-lock phase-locked loop with adaptive bandwidthcontrol

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range     

A monolithic phase-locked loop with post detection processor

Describes the design and fabrication of a high-frequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TTL compatible inputs and outputs.     

A multidimensional phase-locked loop for blind multiuser detection

This paper concerns the problem of blind multiuser detection, a special case of the blind source separation problem in which the source signals have finite alphabets. Specifically, we address the problem of identifying and resolving the n/spl times/n unitary matrix ambiguity U that results from whitening the receiver observations, where n is the number of sources. We propose the multidimensional phase-locked loop (MPLL) as a generalization of a scalar decision-directed PLL to vector-valued signals. The MPLL adapts an estimate of U according to the recursion U/spl circ//sub k+1/=U/spl circ//sub k/R/sub k/, where R/sub k/ is an n-dimensional Householder-like rotation depending on only the kth receiver observation. The O(n/sup 2/) complexity of an efficient implementation of the algorithm is extremely low. Nevertheless, simulation results demonstrate good convergence properties and superior steady-state performance when compared with prior techniques. The algorithm is also able to accommodate large alphabets and shaped alphabets.     

A 2-V, 1.8-GHz BJT phase-locked loop

This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiCMOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 16-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300×4000 μm², including the passive loop filter     

基于FPGA的高性能全数字锁相环设计与实现

本文提出了一种适用范围广泛的全数字锁相环(ADPLL)实现方法,在锁相环输入频率未知的情况下,实现锁相锁频功能.本文从全数字锁相环的基本实现方式入手,进行改进,并使用VHDL语言建模,使用FPGA进行验证.     

一种用于时钟产生的低功耗电荷泵锁相环设计

设计了一种用于时钟产生的电荷泵锁相环(CPPLL),其压控振荡器(VCO)采用了新颖的带电流补偿的电流减法器结构。采用Charted2.5V、0.25μmCMOS工艺,整个芯片的面积为300μm×400μm,VCO输出频率范围为55MHz～322MHz。整个电路功耗低,VCO输出频率为240MHz时,功耗为6mW。Hspice仿真结果表明,VCO输出时钟为96MHz时,峰峰值抖动为320ps。