光学锁相环的研究进展

光学锁相环（OPLL）根据其锁定的两束激光间是否存在频差可分为零差光学锁相环和外差光学锁相环。主要介绍了外差光学锁相环的研究进展,它是一种通过鉴频鉴相方式使激光间的频率差保持相对稳定的偏频锁定方法。相较于其他激光偏频锁定方法,光学锁相环具有结构简单、伺服频率带宽大、频率偏置范围宽、锁定准确度高等优势,在原子相干、冷原子系统、相干功率合成以及外差干涉测量等领域都得到了越来越广泛的应用。首先介绍了激光偏频锁定的主要方法及光学锁相环的特点;其次介绍了光学锁相环的基本模型,分析了光学锁相环的误差反馈过程,并按照光学锁相环实现方法的不同详细介绍了其采用的关键技术和研究进展,对近年来光学锁相环在不同领域的应用进展做了简要介绍;最后对该方法的发展路线进行了总结和展望。     

Optical phase-locked loop for coherent detection optical receiver

A novel subcarrier-based optical phase-locked loop (SC-OPLL/sup /spl reg//), with off-the-shelf optical components, is presented and demonstrated. The method, based on a continuous-wave laser and optical subcarrier modulation using a standard LiNbO/sub 3/ Mach-Zehnder modulator, allows easier practical implementation than the previously proposed OPLL circuits based on laser direct modulation.     

A frequency steered phase-locked loop

Narrow bandwidth phase-locked loops (PLLs) can have difficulty acquiring lock reliably when there is a significant difference between the input signal and the free run frequency of the PLL's voltage-controlled oscillator (VCO). The new technique presented here incorporates an accurate local reference frequency into the PLL structure. The range of frequencies to which the new PLL structure can lock can be confined to a desired small region around the accurate local reference frequency. The new PLL structure also provides other benefits such as reduction of VCO phase noise. The new technique does not require any monitoring nor any switching of the local frequency reference signal which is always acting. The key parameters of the new PLL structure are identified and the performance characterized     

A power-efficient wide-range phase-locked loop

This work presents a phase-locked loop for clock generation that consists of a phase/frequency detector, charge pump, loop filter, range-programmable voltage-controlled ring oscillator, and programmable divider. The phase/frequency detector and charge pump are designed to reduce the dead zone and charge sharing for enhancing the locking performance, respectively. In the design of the range-programmable voltage-controlled oscillator, the original inverter ring of a delay line is divided into several smaller ones, and then they are recombined in parallel to each other. Programming the number of paralleled inverter rings allows us to generate the wide-range clock frequencies. This design shuts off some inverters that are not in use to reduce power consumption. To allow the phase-locked loop to shut off inverters, the feasibility of using controllable inverters by the output-switch and power-switch schemes is explored. Theoretical analyses indicate that power consumption of the voltage-controlled oscillator depends on transistors' sizes rather than operating frequencies. By applying the TSMC 0.35-μm CMOS technology, the proposed phase-locked loop that uses the power-switch scheme can yield clock signals ranging from 103 MHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, power dissipation that is proportional to the number of paralleled inverter rings is measured with 1.32 to 4.59 mW. The phase-locked loop proposed herein can be used in various digital systems, providing power-efficient and wide-range clock signals for task-oriented computations     

一种快速全数字锁相环

本文根据突发式数字通信快速锁相要求,提出一种位同步信号提取的新的快速全数字锁相环方案.它比一般数字锁相环捕捉速度最大可以提高N/2倍,且环路的同步时间与量化相位误差的矛盾也得到了解决,因而环路精度也大有改善.本文主要以一阶环为例讨论位同步信号提取.     

A 2-V amplitude-linear phase-locked loop

An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-/spl mu/m CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier, and a voltage-controlled oscillator control buffer is used to define a linear frequency characteristic. The measured performance demonstrates suitability for portable tone-decoding and FM demodulation applications.     

拉曼激光光学锁相环参数设计及仿真

光学锁相环（Optical Phase-locked Loop,OPLL）技术是实现激光相位相干的有效方法。鉴于环路滤波器参数直接影响光学锁相环系统的整体性能,提出了一种二阶无源环路滤波器参数的优化方法。首先,根据相角裕度定义及系统开环传递函数的数学模型,推导出环路滤波器参数设计的公式,并设计了一种基于MATLAB的参数优化算法。然后,为精确地设计拉曼激光光学锁相环参数,设计了消多普勒饱和吸收谱实验,并对激光器的压电陶瓷端口反馈增益参数进行测量。在锁相环闭环控制系统性能仿真中,得到了单位阶跃响应的超调量为6.53%,调节时间为0.584s。最后,对拉曼激光光学锁相环各个模块进行Simulink建模并仿真,仿真结果表明锁相环能够实现对拉曼光相位锁定且锁定时间为2s,因此,验证了锁相环参数设计方法的正确性。在工程应用中,为光学锁相环的参数设计提供了重要参考价值。     

Heterodyne optical phase-locked loop by confocal Fabry-Periotcavity coupled AlGaAs lasers

Two external confocal Fabry-Perot cavity-coupled 0.83-μm AlGaAs lasers phase-locked to one another by a heterodyne optical phase-locked loop are discussed. The phase error under phase-locking conditions was measured using the square root of the Allan variance. The result confirmed that the heterodyne signal was a full replica of the spectrum of the reference RF signal within the loop bandwidth. The estimated phase-error variance was 0.02 rad², i.e. ≃8.1°     

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively     

A high lock-in speed digital phase-locked loop

A digital phase-locked loop (DPLL) consisting of a modified 9-gate phase detector, a frequency multiplier, and a loop filter is described. All the components are implemented in digital hardware. The Z-transform is employed to deduce the system function, and some simple properties of the DPLL are inferred by examining the mathematical model. The advantages of the proposed DPLL are: high lock-in speed, no steady-state frequency tracking error even for period ramp input signals; and ease of integration into a single chip. The use of the DPLL to realize the pitch synchronous analysis of voiced speech is reported     

注入锁定对激光锁相环性能的影响

本文研究了注入锁定对半导体激光锁相环性能的影响,给出了注入锁定半导体激光器作为激光锁相环本振的相位传递函数及激光锁相环的噪声特性.     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A 2-GHz 1.6-mW phase-locked loop

This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset     

Some analytical and experimental phase-locked loop results for low signal-to-noise ratios

This paper is concerned with the nonlinear behavior of the second-order phase-locked loop (PLL) in the presence of noise. The loop filter is of the proportional-plus-integral control type. This filter corresponds to the one generally employed for carrier tracking purposes in the implementation of phase-coherent communication systems. The paper is composed essentially of two parts: the first part presents analytical results which pertain to the probability distribution of the phase-error. Since these analytical results are approximations, valid only for certain regions of signal-to-noise ratio, they are complemented by experimental results obtained from simulation of the PLL system in the laboratory. The experimental techniques used to measure the statistical properties of the loop behavior and the corresponding results comprise the second part of the paper. Approximate analytical expressions for the distribution of the system phase-error are first obtained by using the Fokker-Planck apparatus and, secondly, by assuming that the PLL behaves as a very narrow band-pass filter. The range of signal-to-noise ratios for which these approximations are valid is obtained by graphically comparing the analytical expressions to experimentally derived phase-error distributions. In addition, measurements relative to the variance of the phase-error are compared to those predicted by the linear PLL theory and the variance as computed from the approximate solutions. Finally, experimental results relative to the probability distribution of the time intervals between cycle-slipping events are given for signal-to-noise ratios in a range where the linear PLL theory does not apply. In particular, the maximum length of time the loop may be expected to remain in-lock is illustrated graphically as a function of signal-to-noise ratio in the loop bandwidth.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

一种基于环形振荡器的双环路锁相环

A dual-loop phase-locked loop（PLL）for wideband operation is proposed.The dual-loop architecture combines a coarse-tuning loop with a fine-tuning one,enabling a wide tuning range and low voltage-controlled oscillator（VCO）gain without poisoning phase noise and reference spur suppression performance.An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized.A novel multiple-pass ring VCO is designed for the dual-loop application.It utilizes both voltage-control and current-control simultaneously in the delay cell. The PLL is fabricated in Jazz 0.18-μm RF CMOS technology.The measured tuning range is from 4.2 to 5.9 GHz.It achieves a low phase noise of–99 dBc/Hz@1 MHz offset from a 5.5 GHz carrier.     

一款通过抗辐照设计加固技术实现的抗单粒子锁相环

本文设计了一款抗辐照设计加固的锁相环。通过增加一个由锁定探测电路、两个运放和4个MOS器件组成的电荷补偿电路,该锁相环显著地减小了单粒子瞬态引起失锁后系统的恢复时间。许多传统的加固方法主要是致力于提高电荷泵输出结点对单粒子瞬态的免疫力,本文的加固方法不仅能够降低电荷泵输出结点对单粒子瞬态的敏感性,而且也降低了其他模块对单粒子瞬态的敏感性。本文还提出了一种新的描述锁相环对单粒子顺态敏感性的系统模型,基于该模型比较了传统的和加固的锁相环对单粒子瞬态的免疫能力。通过Sentaurus TCAD 仿真平台模拟了单粒子瞬态引起的电流脉冲,用于电路仿真。基于130 nm CMOS 工艺设计了两个锁相环电路,晶体管级的仿真表明本文提出的抗单粒子加固锁相环的恢复时间比传统的锁相环提高了94.3%,同时,电荷补偿电路没有增加系统参数设计的复杂性。