一种用于APFC的模拟乘法器设计

在有源功率因数校正技术(APFC)中,通过对乘法器的输出与电感电流的峰值比较,控制功率开关管的开启与关断,使输入电流峰值包络跟随输入电压,功率因数理论上为单位值。而提高乘法器的线性度,减小非线性误差成为研究模拟乘法器的一个重要方向。本文提出的模拟乘法器采用有源衰减器显著的增大了输入信号电压范围,更重要的是在有源衰减电路中引入负反馈有效的减小了乘法器的非线性误差。基于CSMC 0.5um BCD工艺,采用Hspice进行仿真验证,在电源电压5V条件下,乘法器的一输入端的输入范围为0~2V,非线性误差小于0.6%,另一输入端的输入范围为1~4V,非线性误差小于0.3%。总谐波失真小于1.8%。     

一种用于THD优化的模拟乘法器设计

为有效地提高有源功率因数校正控制器(APFC)[1]性能,设计了一种用可控电流法实现,可应用于连续/临界型(CCM/DCM)升压(BOOST)模式APFC的模拟乘法器.该乘法器有较好的线性特性,线性范围达到0~3V,与传统方法相比,特别嵌入了总谐波失真(THD)优化电路,从而达到最优化输入电流THD,提高功率因数的目的.最后给出了具体的乘法器电路图和仿真结果.     

一种宽输入范围的Gillbert模拟乘法器设计

本文分析了基于CMOS工艺设计的Gillbert单元乘法器,改进了原有电路工作电压高的缺陷,使它能在更低的电源电压下工作,并在乘法器的输入级加入有源衰减电路,增大乘法器的输入范围。本文采用上华0.6μmCMOS工艺进行设计,并用Cadence Spectre仿真器对电路进行了仿真,得到3V电源电压下,输入范围为0～2V的模拟乘法器。     

一种CMOS四象限模拟乘法器的设计

本文提出了一种CMOS四象限模拟乘法器。这种乘法器基于MOS晶体管的电流-电压平方关系,采用线性MOS跨导器、悬浮电压发生器和线性MOS电阻完成乘法运算。这种乘法器具有单端输出电压和较好的温度特性。文章比较详细地介绍了电路特点和工作原理,分析了电路的温度性能,并给出了SPICEⅡ的模拟结果。     

一种高性能的CMOS四象限模拟乘法器

本文介绍了一种带预处理电路的ＣＭＯＳ四象限模拟乘法器，对其预处理电路（有源衰减器及电平位移电路）和乘法器核心电路的非线性误差作了详细的讨论．设计采用３微米Ｎ阱硅栅ＣＭＯＳ工艺，并给出了电路的ＳＰＩＣＥ模拟结果．当电源电压为±５Ｖ时，功耗小于６．５ｍＷ，线性输入电压范围约为±４Ｖ；当输入电压范围限于±３Ｖ内时，总谐波失真和非线性误差均小于０．３３％，－３ｄＢ带宽为１３．０ＭＨｚ和２．２ＭＨｚ；当输入电压范围限于±２Ｖ内时，总谐波失真小于０．１８％，具有良好的性能．     

一种低压高线性CMOS模拟乘法器设计

提出了一种新颖的CMOS四象限模拟乘法器电路．该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0．18μmCMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1．8V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0．3V,-3dB带宽可达到1GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

模拟乘法器的应用

介绍了模拟乘法器在混频器中的典型应用，它可提高电路的载波抑制比，扩展输入信号的线性动态范围，对不同型号的模拟乘法器的性能进行了对比。     

一种新型低压COMS四象限模拟乘法器

提出了一种采用有源衰减器和全差分电流传输器(FDCCⅡ)为核心的新型低压CMOS四象限模拟乘法器.PSPICE仿真表明,当电源电压为±1.5 V时,电路功耗小于75μW.该乘法器电路具有较好的线性输入范围,达到±1 V,当输入电压范围限于±0.8V时,非线性误差小于0.6%,-3 dB带宽约为10 MHz.     

一种高线性度低失真模拟乘法器的设计

基于吉尔伯特单元,设计了一款高线性度低失真模拟乘法器.通过在输入端加入一个电平移位器,使线性输入范围增大,并由一个跨导运算放大器给吉尔伯特单元提供尾电流,有效地改善了乘法器的线性特性.设计的电路基于UMC 0.6μm BCD工艺,采用HSPICE进行仿真验证.结果表明,该乘法器的线性输入范围可达±2 V,非线性误差和总谐波失真分别小于1%和0.3%,适用于要求输入范围大、非线性误差小及失真低的系统.     

An analog multiplier

A different approach to analog multiplication results in a four-quadrant multiplier using a field-effect transistor FET in a feedback network. The linear multiplication is obtained by operating the FET as a voltage-controlled conductance.     

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 μm CMOS process. Experimental results obtained from it are presented     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.     

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.     

基于模拟乘法器的温度传感器线性化设计方法

利用模拟乘法器独特的运算功能,分别给出热电偶、热敏电阻、铂热电阻测温电路线性化的设计方法。该方法简单,可从根本上消除非线性误差,准确度高,对电路和环境要求低,适用于高精度宽范围的仪器仪表,应用表明效果较好。     

Single-ended-input single-ended-output four-quadrant analog multiplier

Modifications are made to Gilbert's product-quotient circuit to achieve a true four quadrant multiplier with transposed origin. The modified circuit can be easily fabricated in integrated form and has the desirable features of single ended input and output.     

Feedback stabilized four-quadrant analog multiplier

A technique utilizing an ideal controlled current fork as a fundamental building block is evolved to generate the product of two variables. A particularly useful implementation of the technique, making use of the exact exponential characteristics of the emitter-base junction of the bipolar transistor to realize a controlled current fork, is demonstrated. It is shown that a mismatch of transistor pairs and a mismatch of resistance values give rise to certain predictable errors for which quantitative expressions are derived in order to determine acceptable tolerances. Measurements on a particular design are given to support the theoretical derivations, and the operation of the multiplier as a squarer, independent of transistor-pair mismatch, is demonstrated.     

A low-power CMOS analog multiplier

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.     

A mask-programmable charge-transfer analog multiplier

A mask-programmable four-quadrant multiplier where an analog multiplication coefficient is stored at each stage of a serial charge-transfer device is described. A serial stream of input data samples d/SUB n/ is multiplied by coefficients c/SUB n/ and sequentially produces an output stream of signal samples c/SUB n/d/SUB n/. Since input and output are both serial and the multiplication coefficients are stored on-chip, the device is ideally suited for performing the pre- and postmultiplication required in a charge-transfer device implementation of the chirp z-transform. Experimental results using this device in conjunction with fixed tap weight transversal filters to perform the chirp z-transform are presented. An architecture for a single-chip spectrum analyzer based on the chirp z algorithm is presented.