An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

Boron ion implantation in silicon through selectively deposited tungsten films

The effect of implanting boron into silicon through thin selective tungsten films and annealing to form silicided p⁺-n junctions is investigated. A rate limited thickness of 0.011-µm tungsten is shown to have the equivalent stopping power of 0.08-µm oxide and be similarly ineffective in eliminating axial boron channeling. Nonetheless, junction diodes as shallow as 0.25µm with sheet resistances of 7 Ω, exhibiting nearly idealI-Vcharacteristics from -40 to 100°C, are fabricated. Analysis of the areal and perimeter leakage currents suggests that defects at the WSi2-SiO2interface are the contributing generation-recombination sites.     

Enhanced mobility top-gate amorphous silicon thin-film transistorwith selectively deposited source/drain contacts

Amorphous silicon thin-film transistors (TFTs), in a top-gate staggered electrode structure have been prepared using selectively deposited doped silicon contact layers, formed in-situ by plasma-enhanced chemical vapor deposition (PECVD). Selective deposition reduces the number of processing steps and assures the formation of low-resistance contacts. Devices fabricated with two photomasks and one plasma deposition step show saturation and linear mobilities as high as 1.1 and 0.9 cm²/V-s, respectively, with threshold voltages between 3 and 6 V. On/off ratios are >10⁶, with a subthreshold slope of 0.8 V/decade. The mobilities are at least a factor or 2 higher than previously reported for top-gate structures and are similar to values reported for bottom-gate (inverted staggered) TFTs     

High-frequency power MOSFETs fabricated using selectively deposited LPCVD tungsten

A novel high-density, high-frequency power MOSFET structure fabricated using selectively deposited LPCVD tungsten on gate polysilicon and source contact regions is reported. The gate-to-source isolation was provided by anisotropically etched phosphosilicate glass (PSG) spacers. Using this technology, the author has successfully fabricated 30 V power DMOS FETs with excellent high-frequency switching performance in terms of low specific on-state resistance R/sub sp/=0.5 m Omega cm/sup 2/, low specific input capacitance C/sub sp/=43 nF/cm/sup 2/, and high switching speed: t/sub on/ and t/sub off/<2 ns. These results represent the first successful demonstration of complex device structures fabricated using LPCVD tungsten derived process technology.<>     

A twin-well CMOS process employing high-energy ion implantation

A twin-well CMOS process has been developed using ion implantation with energies up to 1 MeV. The high-energy ion-implantation steps eliminate the need for extended processing times at high temperatures. As a consequence, this permits an increase in packing density, independent control of critical electrical parameters, and simplified processing. The resulting process includes advantages of recent developments in bulk CMOS: an n-type isolation well in a p-p⁺substrate and retrograde wells. This paper discusses the processing steps involved and provides the resulting device characteristics. An interesting application of the process is also presented, which is the realization of a gate array with TTL-compatible input and output buffers.     

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.     

A simple punchthrough voltage model for short-channel MOSFET's with single channel implantation in VLSI

Based on the step-profile approximation and geometrical analysis, the punchthrough voltage of short-channel enhancement n-channel MOSFET's with single channel implantation has been derived by defining a punchthrough depth. The punchthrough depth, which represents the distance of the two-dimensional potential ridge from the SiO2-Si interface, is calculated by the surface potential of the punchthrough point. Therefore, the derived punchthrough voltage model is then analytically expressed in terms of device geometries and implant parameters. Comparisons between the developed model and the experimental devices have been made and excellent agreement has been obtained.     

Electrical and structural properties of diodes fabricated in thick,selectively deposited Si/Si1-xGex epitaxial layers

The characteristics of diodes fabricated in thick Si_1-xGe_x layers formed by selective epitaxial deposition have been examined by DC electrical measurements, transmission electron microscopy, and X-ray topography. Because depositing in restricted areas limits the propagation of misfit dislocations in thick layers, a lower misfit dislocation density is found in small-area deposited regions. Similarly, diodes fabricated in small deposited regions have more ideal forward characteristics than diodes fabricated in large regions     

A joint source/channel coder with block constraints

The assumptions made about the source during source coder design result in a residual redundancy at the output of the source coder. This redundancy can be utilized for error protection without any additional channel coding. Joint source/channel coders obtained using this idea via maximum a posteriori probability decoders tend to fail at low probability of error. In this paper, we propose a modification of the standard approach which provides protection at low error rates as well     

Hole mobility enhancement of pMOSFETs with strain channel induced by Ge pre-amorphization implantation for source/drain extension

A simple, highly manufacturable process has been demonstrated to induce a uniaxial compressive stress in the channel to gain enhanced pMOSFETs performance without additional mask. By integrating Ge pre-amorphization implantation (PAI) for S/D extension of pMOS device, up to 32% hole effective mobility improvement has been obtained comparing control one at 0.6 MV/cm vertical field, and the hole mobility enhancement is nearly kept at higher vertical field. The scaling of feature size, such as gate length and channel width, strengthen the enhancement of the hole effective mobility greatly. The electron effective mobility has a negligible affection.     

Multiple ion implantation profile using differential channel dose

Multiple ion implantations are frequently used, especially for extension regions in high-speed MOSFETs, to ensure symmetrical doping profiles. In the process simulation, each process step is treated independently and the final impurity concentration after the multiplied ion implantation is linearly multiplied by the number of first-implantation processes. However, as the channeling tail of the ion implantation profile is saturated in high dose regions, the simple multiplication of the profiles induces artificial deeper junction depths. To solve this problem, we introduced a differential channel dose, which enables us to generate accurate ion implantation profiles, and here we will demonstrate that the conventional treatment of the multiple ion implantations predicts worse short channel effects especially for nMOSFETs.     

Short channel Ga0.47In0.53As/Al0.48In0.52As selectively doped field effect transistors

We report a selectively doped Ga0.47In0.53As/Al0.48In0.52As field effect transistor with a 1.2 µm gate length and present a model of two-region operation to analyze its I-V characteristics. This depletion mode transistor shows complete pinch-off and saturation characteristics with a low frequency transconductance of 70 mmho/ mm at 300 K and 125 mmho/mm at 77 K. The theoretical model, which includes the background carriers in the undoped Ga0.47In0.52As layer, agrees with the experimental results.     

Self-aligned AlGaAs/GaAs HBT with selectively regrown OMVPE emitter

A self-aligned HBT mesa fabrication process utilizing selective organometallic vapor phase epitaxy (OMVPE) is reported whereby the extrinsic base has been made considerably thicker than the intrinsic base, thus avoiding the conventional tradeoff between base resistance and base transit time. This technique also simplifies processing by eliminating the need for emitter isolation by etching or ion implantation prior to base metallization. Application of this process to AlGaAs/GaAs N-p-n HBTs has yielded an intrinsic to extrinsic base sheet resistance ratio of 1.5, an f_T of 22 GHz, and an f_max of 55 GHz     

Performance and hot-carrier reliability of 100 nm channel lengthjet vapor deposited Si3N4 MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si₃N₄ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO₂ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si₃N₄ barrier (2.1 eV) is lower than the Si-SiO₂ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO₂ MOSFETs     

Multiple Sb ion implantation for deep-submicron pMOS channel doping

We propose a channel doping technology for pMOSFET's in which Sb is multiply ion implanted to produce a uniform doping profile in the region deeper than the minimum projected range of the multiple ion implantation. We derive a threshold voltage model and show how to realize this uniform doping profile, which is verified with experimental data. We study the short-channel effect of this device using a two-dimensional (2-D) device simulator, and show that this transistor can readily operate with a gate length of down to 0.1 μm     

A silicon carbide LOCOS process using enhanced thermal oxidation by argon implantation

A process is described for creating local oxidation of silicon structure (LOCOS) structures in silicon carbide using enhanced thermal oxidation by argon implantation. Thicker oxides were created in selective regions by using multiple energy argon implants at a dose of 1 × 10¹⁵ cm⁻² prior to thermal oxidation. Atomic force microscopy was used to analyze the fabricated LOCOS structure.     

A 21-ns 32 K/spl times/8 CMOS static RAM with a selectively pumped p-well array

The design and performance of a 32 K/spl times/8-b CMOS static RAM (SRAM) are presented. The design features a selectively pumped p-well array. Using this array technology, high-impedance polysilicon resistor loads can be used to reduce the array standby current by three orders of magnitude, and the device characteristics can be optimized to achieve high speed in the peripheral circuits. A unique divided-word-line architecture with shared sense amplifiers is used to achieve high-speed read operation. The read speed is further enhanced by a novel quasistatic equalization that minimizes peak current. A high-speed write circuit with a write-to-read transition detection is used to achieve a fast write operation. An advanced 1.2-/spl mu/m double-level-metal CMOS technology was used to fabricate the devices. The access time is 21 ns and the active power is 330 mW at 22 MHz.     

Poly I2L with deposited polysilicon collector

A new high speed high density poly I²L structure with deposited polysilicon collector is analyzed and modeled. The switching speed of the proposed poly I²L structure is 4 times higher than that of the conventional structures and the packing density is improved by a factor of 2.The proposed poly I²L structure is gnvestigated using a developed computer simulation model. Parameters sensitivity analysis of the structure is given. The minimum gate delay decreases as the intrinsic base sheet resistivity is increased and as the thin epitaxial layer under the base is decreased. Down scaling effects are discussed. It is shown that a lateral shift of PDP curves along the current axis is proportional to the change in the device area and the IR drop in npn base is proportional to the scaling factor.A structure with technology linewidth L = 2.5 μm exhibits minimum gate delay of 0.6 ns at 150 μA for fan-out F = 3, and a power-delay product of 30 fJ at low current levels. Simulation results are compared with experimental measurements performed on a given poly I²L structure and good agreement has been observed.     

Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation

Excellent n-channel poly-Si thin-film transistors (poly-Si TFTs) have been formed by using retrograde channel scheme with channel doping implantation and extra counter-doping implantation. As compared to the conventional sample with undoped channel layer, a much smaller leakage current can be achieved by boron-doping the poly-Si channel layer, due to a significantly reduced depletion region. However, the on-state characteristics are degraded. A retrograde channel scheme, implemented by further phosphorus counter-doping the surface of the boron-doped channel layer, is proposed for lowering the channel surface doping concentration without changing the bulk channel doping concentration. By using the retrograde channel scheme, an off-state leakage current as low as that for the normal channel-doping scheme may be achieved, while yielding excellent on-state I-V transfer characteristics.     

A selectively contacted dual-channel HEMT

A dual-channel high-electron-mobility transistor (HEMT) with selective contacts to each channel is discussed. The conduction properties of each individual channel are obtained using simple DC measurements. Isolation between the channels and the presence of the kink effect are discussed. In addition, inverter-like behavior from a single device is obtained at 77 K