Aerial edge computing for 6G

In the 6 th generation mobile communication system(6 G) era, a large number of delay-sensitive and computation-intensive applications impose great pressure on resource-constrained Internet of things(IoT) devices. Aerial edge computing is envisioned as a promising and cost-effective solution, especially in hostile environments without terrestrial infrastructures. Therefore, this paper focuses on integrating aerial edge computing into 6 G for providing ubiquitous computing services for IoT devices...     

The impact of supercomputers on IC technology development and design

Very large scale integration (VLSI) has evolved at an enormous rate, progressing from hundreds of components on an integrated circuit (IC) in the 1960's to a million components on a chip in the foreseeable future. This paper reviews some of the computer-aided design (CAD) tools that are essential for VLSI technology development and circuit design and that also require large amounts of computer resources. Specifically, we describe programs for process simulation, device simulation, and circuit simulation. This paper also reviews the impact of high-performance computing facilities on the development and use of these programs at AT & T Bell Laboratories.     

Nonlinear Data Utilization: From Direct Data Lookup to Behavioral Modeling

This paper presents a comprehensive study on the effective utilization of large-signal measurement data in the nonlinear computer-aided design (CAD) process. To achieve this goal two distinctive, yet mutually complementary, approaches have been integrated. Measured nonlinear data was, in the first instance, directly integrated into a nonlinear CAD simulator, and in the second instance, utilized for a direct extraction of behavioral model parameters. The formulation of the developed model is based on the polyharmonic distortion approach. The combination of both the direct utilization of nonlinear data and the subsequent model generation into an integrated nonlinear design procedure offers rapid, yet reliable, deployment of the CAD-based design environment for complex large-signal simulations.      

协同集成设计环境的通信支持若干问题研究

首先提出了一种直接建立在现有CAD应用内核之上的进程间通信模型,并通过实验研究对此进行了验证。然后提出了支持协同集成设计的通信协议集的一种基本框架。最后研究了对工程中大规模复杂CAD图形数据进行协议映射和动态传输的基本方法。实践证明,比现有交换数据文件和传输应用界面方法,在网络通信的时间/空间效率上具有显著优势。*     

Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design

Validation of an System-on-Chip (SoC) design with networking capability needs global simulation of the whole system including the network as well as the SoC design itself. Especially, it is needed to validate the interoperability of SoCs from different vendors. In this paper, we propose a simulation environment and simulation techniques for efficient validation of such SoC designs and apply them to networked Bluetooth SoC designs. The environment enables two types of simulation. One is modular enough to include the simulation of other vendors' Bluetooth devices and the other is optimized to achieve fast simulation in developing in-house Bluetooth devices. Especially, the former is scalable in that it keeps the constant simulation runtime despite the increase of the number of Bluetooth devices. Since multiple simulators are involved, the global simulation is still slow. Thus, the simulation efforts need to be minimized to shorten the design cycle. We present two simulation techniques, a concept called grouped message for reduction in simulation runtime and a system debug scenario called fix–modify–restart for reduction in the number of simulation runs. The former is to reduce inter-process communication overhead between simulators in the global simulation. The latter is to reduce repeated simulation runs in the conventional design cycle. Experimental results show the scalability of the presented simulation environment, reduction in simulation efforts by two simulation techniques.     

Self-Configuring Applications for Heterogeneous Systems: Program Composition and Optimization Using Cognitive Techniques

This paper describes several challenges facing programmers of future edge computing systems, the diverse many-core devices that will soon exemplify commodity mainstream systems. To call attention to programming challenges ahead, this paper focuses on the most complex of such architectures: integrated, power-conserving systems, inherently parallel and heterogeneous, with distributed address spaces. When programming such complex systems, new concerns arise: computation partitioning across functional units, data movement and synchronization, managing a diversity of programming models for different devices, and reusing existing legacy and library software. We observe that many of these challenges are also faced in programming applications for large-scale heterogeneous distributed computing environments, and current solutions as well as future research directions in distributed computing can be adapted to commodity computing environments. Optimization decisions are inherently complex due to large search spaces of possible solutions and the difficulty of predicting performance on increasingly complex architectures. Cognitive techniques are well suited for managing systems of such complexity, citing recent trends of using cognitive techniques for code mapping and optimization support. Combining these, we describe a fundamentally new programming paradigm for complex heterogeneous systems, where programmers design self-configuring applications and the system automates optimization decisions and manages the allocation of heterogeneous resources.     

云计算环境下计算机网络安全分析

随着云计算技术的发展，越来越多的企业和机构开始采用云计算技术来实现资源共享和灵活部署。然而，云计算环境下的网络安全问题日益凸显。如何保障云计算环境下的网络安全，成为当前亟待解决的问题。文中从多个方面探讨了云计算环境下计算机网络安全管理的保障策略，以期为相关企业和机构提供参考。     

A guide to engineering workstations: using workstations efficiently

The development of a distributed computing environment that ties together diverse design operations is discussed. A vast array of computer-aided engineering tools and related software is being integrated into a fully distributed, data-driven environment called the Grumman Computer/Information Integrated Enterprise (CIE). The decision was made to maintain Grumman's CAD/CAM capabilities while controlling operating costs through effectively linked workstations. Crucial to the plan is the definition and implementation of a local-area network (LAN) strategy to link all the different types of machines together. The network tasks are defined, the current set-up is described, and past problems are reviewed. The plan for migration to an integrated electronic design system based on lower-cost, high-powered workstations operating in an open-architecture environment is discussed. An accompanying table gives an extensive sampling of commercially available workstations     

High-performance automatic target recognition through data-specificVLSI

Under the Mojave configurable computing project, we have developed a system for achieving high performance on an automatic target recognition (ATR) application through the use of configurable computing technology. The ATR system studied here involves real-time image acquisition from a synthetic aperture radar (SAR). SAR images exhibit statistical properties which can be used to improve system performance. In this paper, the Mojave configurable computing system uses field programmable gate arrays (FPGA's) to implement highly specialized circuits while retaining the flexibility of programmable components. A controller sequences through a set of specialized circuits in response to real-time events. Computer-aided design (CAD) tools have been developed to support the automatic generation of these specialized circuits. The resulting configurable computing system achieves a significant performance advantage over the existing solution, which is based on application specific integrated circuit (ASIC) technology     

On‐Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.     

Planar packaging of free-space optical interconnections

Planar optics is an approach to build integrated free-space optical systems on single substrates. Computer-aided design, lithographic fabrication, and micro-bonding techniques are used to package the optics in a compact way. This paper reviews recent work on planar optics. It discusses various aspects of the fabrication, the design, and the application of planar optics as an interconnection technology for optoelectronic computing and switching systems     

Care in the Community

This paper considers the application of pervasive computing to the provision of care in the community, specifically older frail people living alone in their own homes. The concept of well-being is introduced and developed through the explanation of a conceptual framework that incorporates person, context and experiential factors. The paper reviews how different aspects of well-being might be instrumented within the home of an older person using non-intrusive pervasive sensors and computing devices. The data acquired from these sensors can be used to describe a model of behaviour for each individual. It is proposed that long-term drifts in well-being, that might be early indicators of an underlying physical or psychological condition, can be detected by analysing subtle changes within the behavioural model. The objective of such a system is to provide the stakeholders involved with an intuitive early warning system in order to facilitate appropriate intervention by care providers leading to a reduction in the cost of care to the state and increased quality of life for the individual.The domain of social care provision in the UK is described in detail, including an analysis of local authority social services referral procedures, and suggestions made as to the role of well-being monitoring for such service providers. Ethical issues have been addressed by explicitly coding choices about sensor types and their usage into the system design tool. System deployment issues are discussed including installation processes, service provision, and functional specification which lead to the key technical challenges that must be overcome for low-cost pervasive systems to become a practical reality across all local authorities in the UK.     

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.     

一种Linux下动态内存泄漏检测技术的实现

内存泄漏是软件开发中经常遇到的问题。在使用C/C 开发的大型软件中,内存泄漏往往很难发现。现介绍了一种基于动态代码插装技术的内存泄漏检测器的实现方法。该方法在实践中证明简单易用,对软件运行期内的影响较低。     

面向算力网络的IP承载网关键技术及网络部署策略研究

随着云计算、边缘计算和智能终端的快速发展,算力资源呈现出泛在部署趋势,算力网络能够通过灵活的承载网络对泛在异构的算力资源进行调度,有效提升了算力资源利用率。文中结合当前算力网络发展现状,对算力网络的概念定义以及标准体系进行了总结,随后对SDN,SRv6等算力网络关键承载技术进行了阐述,并讨论了其在算力网络中的典型部署策略,最后对算力网络面临的挑战与后续研究方向进行了展望。     

A soft-systems methodology approach for product and processinnovation

Soft-systems methodology (SSM) has been recommended as a tool for scientifically evaluating complex environments. One such environment is the development of organizational processes and products delivered by organizations. This paper proposes a methodology for organizational product and process innovation based on SSM theory incorporating quality function deployment (QFD) and IDEF0 (integrated definition functional modelling tool) techniques. The methodology relies on a series of phases that elicit information from complex and amorphous real-world practices, processes, and information, and develops models of these systems. The paper illustrates the utility of the methodology and tools using a case example: development of an organizational decision support system used to justify strategically important technologies for the enterprise     

Disconnected Processes, Mechanisms and Architecture for Mobile E-Business

With the tremendous advances in hand-held computing and communication capabilities, rapid proliferation of mobile devices, and decreasing device costs, we are seeing a growth in mobile e-business in various consumer and business markets. In this paper, we present a novel architecture and framework for end-to-end mobile e-business applications (e.g., point of sales). The architecture takes into consideration disconnection, application context, synchronization, transactions and failure recovery modes to provide mobile users with seamless and transparent access to business transactions and business-context specific data. In our architecture, we consider a novel business process design based on state-machines and event management to handle disconnection, resource limitations and failures. We designed, implemented and deployed a system for mobile e-business on clients (e.g., PDAs and PocketPCs) integrated with private exchanges and sell-side servers. The state-machine model with failure recovery mechanisms enables handling of one-to-many and many-to-one disconnections in large mobile e-business environments. The e-business framework on mobile clients is implemented based on J2ME, Webservices, and open XML standards. A detailed performance study of commerce transactions was done on different mobile client devices with diverse computing, memory and storage capabilities. We compare the performance of a purchasing application and the middleware on various devices such as PDAs and Laptops. We demonstrated that for small devices with limited capability the performance is reasonable. For devices with more computing capability, the response time is excellent.     

First Silicon Functional Validation and Debug of Multicore Microprocessors

Microprocessor designs are increasingly moving towards multiple cores on a single die. Validating memory consistency, coherency, ordering, and atomicity is crucial. X86 microprocessors are prevalent at most levels of computing. Thus, new x86 microprocessors undergo extensive compatibility testing. Being a high volume product, the economic and logistical repercussions of a functional deficiency escaping into the production cycle and beyond are humbling. The first silicon functional validation and debug of multicore microprocessors are constrained by design complexity, compatibility with existing hardware and software, and time-to-market pressures. This paper describes microprocessor debug features and their use in debugging functional failures. An encompassing overview of the microprocessor's first silicon validation is presented. Emphasis is put on validation and debug of multicore microprocessors targeting multinode systems. This paper presents a novel method to validate and debug intra-node and inter-node communication traffic. This paper also develops an analysis to determine optimal on die debug resources. Finally, data from an 8-node system is presented to demonstrate the extent of intrusiveness of a coherent and noncoherent traffic debug feature