Hot-electron effects in Silicon-on-insulator n-channel MOSFET's

Hot-electron degradation has been measured in short-channel bulk and SOI MOSFET's. The presence of a floating substrate in the SOI devices appears to increase the drain-saturation voltage and, therefore, to reduce the drain electric field. This effect is even further enhanced when thin fully depleted films are considered. Electrical stress measurements and device modeling suggest that hot-electron degradation should be smaller in SOI MOSFET's than in their bulk counterparts.     

Hot-electron induced excess carriers in MOSFET's

The existence of minority carriers in the substrate of n-channel MOSFET's operating in the saturation region is shown to be induced by turn-on of the source-substrate junction and photon generation. The two mechanisms are demonstrated experimentally and the photon-generation mechanism is further illustrated on a p-well CMOS wafer. Photon generation poses a constraint in VLSI dynamic RAM design.     

A simple model for short channel MOSFET's

A model for short channel MOSFET's is presented. The model is simple in spite of taking 2-dimensional (2-D) effects into account. Predicted I-V characteristics are in good agreement with experimental results. This model can be utilized in circuit analysis programs.     

Reduction of the reverse short channel effect in thick SOI MOSFET's

We show that the reverse short channel effect (RSCE) is reduced in NMOS devices made in thick silicon-on-insulator (SOI) material. The reduction of the RSCE depends on the thickness of the Si overlayer. It is found that the thinner the Si film, the less the threshold voltage roll-on. The experimental findings are explained by a decrease of the lateral distribution of silicon interstitials generated at the source and drain (S/D) region and are related with their high recombination velocity at the buried oxide. This method can be used to separately test the influence of S/D point defects on the RSCE from other different hypotheses reported in the literature. Coupled process-device simulation reveals that the method is very sensitive to fundamental point defect properties     

Estimation of doping profiles in short channel MOSFET's using DC Measurements

Estimation of impurity profiles in short channel enhancement-mode MOSFET's using the dc measurement technique is studied. The use of long channel theory predicts erroneous impurity profiles for devices with channel lengths of less than 6 µm. A new empirical model for substrate charge sharing is presented which provides good agreement between profiles estimated by measurements on identically doped long and short channel MOSFET's. It is found that the dc measurement technique can be extended to enhancement-mode MOSFET's with channel lengths as small as 2.5 µm.     

Hot-electron limited operating voltages for 0.8-µm MOSFET's

The maximum allowable operating voltage limited by hot-electrons for 0.8-µm MOSFET's, VGS= VDS, is determined to be 5.5 V at room temperature with VSUB= -2 V, as a result of long-term stress aging. Slow and fast threshold-voltage shifts are observed depending on stress conditions, i.e., the amount of hot-electrons injected into the gate SiO2. Generation of interface trapped charges at the Si-SiO2interface near the drain junction is suggested as a main cause for degradation.     

Sub-threshold leakage currents in weakly inverted short channel IGFETS

This paper attempts to develop a comprehensive device model suitable for computer aided design, in the sub-threshold mode of operation, for short-channel insulated-gate field-effect transistors (IGFETs). It is shown that, for state-of-the art MOS LSI, employing 4–6 μ channel length devices, the sub-threshold conduction current is influenced by the longitudinal electric field to a significant degree. The device model is found to be in close agreement with experimental data. The limitations of this model for very short channel IGFETs is briefly discussed.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

甚短距离光传输中保护和错误检测通道的实现

简要介绍了甚短距离VSR4-01.0光传输系统,通过实现保护通道和错误检测通道的功能,以确保光纤数据传输的正确性．采用Verilog HDL语言设计保护通道和错误检测通道,并进行了仿真．选用Altera公司的Mercury EP1M350F780C5 FPGA芯片进行了逻辑功能的仿真和验证。     

Mobility degradation in very thin Oxide p-channel MOSFET's

The effective hole mobility in large-area p-channel MOSFET's decreases systematically over a wide range of oxide fields as the gate oxide thickness decreases from 240 to 31 Å. A scattering mechanism based on the variations of the gate-charge-induced Coulomb scattering potential in the channel resulting from gate oxide thickness and/or structural fluctuations over the gate area is proposed to explain the results.     

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of theG/omegaversus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.     

Width dependence of substrate and gate currents in MOSFET's

Width dependence of hot-electron currents in MOSFET's fabricated with LOCOS, non-LOCOS, and a modified LOCOS processes are studied. The experimental results show that the substrate and gate currents are apparently enhanced in narrow width devices. The enhancement, however, is due to different voltage drops across the source-drain series resistance. The voltage drops are usually larger in wider devices. After correcting for the resistance effect, the substrate and gate currents scale with the device width. With this typical LOCOS process, the bird's beak and in-diffusion of field implant dopants do not cause excess hot-electron activities along the channel/field edges as has been suspected. Some other LOCOS process could, of course, produce a different result. Studies using wide test devices must consider the series resistance effect. With this precaution taken, models derived from wide-channel data will be applicable to narrow-channel devices, at least for some processes.     

Submicron channel MOSFET's logic under punchthrough

The characteristics of n-channel MOSFETs that make use of the punchthrough current are considered in this paper. The current conduction mechanisms of the short channel MOSFET under the bias condition of punchthrough have been studied through the use of two-dimensional computer simulation. Experimental devices with channel lengths as short as 0.5 /spl mu/m were fabricated on a lightly doped substrate. Current-voltage curves of these devices showed pentode-like characteristics for smaller drain biases and triode-like characteristics for larger drain biases. A switching delay as small as 75 ps was obtained for a 13-stage ring oscillator composed of the submicron channel devices.     

On the reverse short channel effect in deep submicronheterojunction MOSFET's and its impact on the current-voltage behavior

In this paper, we report on the reverse short channel effect (RSCE) in vertical heterojunction MOSFET's, which use a source/channel heterojunction for reduction of the short channel effect (SCE) in deep submicron devices. The study shows that a typical RSCE will occur when the heterobarrier dominates the channel potential and when the barrier is strong enough to shift the potential maximum (pMOS) or minimum (nMOS) toward the source/channel interface. The particular channel potential for these devices will give rise to a current-voltage (I-V) behavior which deviates from the classical linear or saturation regime for homojunction devices. A distinctive “transition zone” needs to be taken into account     

Novel technique for measurement of MOSFET threshold voltage at very low channel currents

A curve tracer reveals a low-level current `spike? in the gate-source characteristic of enhancement-mode MOSFETs. The origin of this spike is explained, and its use in measuring the threshold voltage of any MOSFET at a vanishingly small channel current is described. The technique also identifies whether the MOSFET is n-channel or p-channel, enhancement-mode or depletion-mode.     

Inversion-layer capacitance and mobility of very thin gate-Oxide MOSFET's

Inversion-layer capacitance has been experimentally characterized and identified to be the main cause of the second-order thickness-dependence of MOSFET characteristics. Field-dependent channel mobilities of both electrons and holes were independent of gate-oxide thicknesses from 50 to 450 Å, e.g., there is no evidence of the alleged mobility degradation in very thin gate-oxide MOSFET's. Subthreshold slope, insignificantly affected by the inversion-layer capacitance, follows the simple theory down to ∼ 35 Å of oxide thickness. The empirical equations for inversion-layer Capacitance and mobilities versus electric field are proposed.     

Extraction of metallurgical effective channel length in LDD MOSFET's

A new extraction method of metallurgical effective channel length (L/sub met/) in LDD MOSFET's is proposed. This method is based on the clear device physics. First, the carrier density modulation effect is overcome by "paired V/sub TH/" method. Second, the effect of charge sharing is eliminated by extrapolating L/sub eff/ found by "paired V/sub TH/" method to that at zero depletion width between the lightly doped region and the substrate. Both simulation and experimental results demonstrate the accuracy and usefulness of our approach. For example, the device simulation result shows that the extracted L/sub met/ has only 60 /spl Aring/ error compared with the physical dimension defined by the distance between the source and drain n/sup -/ metallurgical junctions. Proposed method is accurate, reliable enough to be used for the routine monitoring in manufacturing environment.<>     

Channel potential and channel width in narrow buried-channel MOSFET's

A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results.     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices