射频CMOS工艺中片上螺旋变压器的新型等效电路模型

本文提出一种新型的紧凑模型来模拟片上螺旋变压器的性能。传统的变压器模型一般都是两个螺旋电感模型的组合,即两个相互耦合的pi型或双pi型子电路的组合。本文所提出的新模型则采用T拓扑结构的形式,虽然它只包含12个集总元件,但是能够精确模拟整个变压器结构的特性。该新型模型具有较强的物理意义,同时文中给出了该模型的具体推导过程。另一方面,本文提出一种简单的参数提取步骤,利用这个提取步骤可以十分容易地提取出新型模型中的所有模型参数,并且不需要计算机的优化拟合。在这个提取步骤中,一个新方法被提出用来提取阶梯电路的参数,而阶梯电路被广泛用于模拟各种无源器件中的趋肤效应。为了检验该新模型的有效性和准确性,本文比较了模型仿真和实际测试在自感、品质因数、耦合系数和插入损耗等方面的特性,在自谐振频率以内的很宽频率范围内,两者均吻合得很好。     

Equivalent circuit model extraction of flip-chip ball interconnects based on direct probing techniques

This letter describes a novel equivalent circuit model extraction approach for flip-chip ball interconnects based on a direct probing techniques. The derived model has been verified up to 40 GHz.     

Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.     

De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20 GHz.     

Equivalent circuit model for arrays of square loops

Square-loop arrays are of interest as frequency selective surfaces. Experimental results for these arrays are presented, and a simple equivalent circuit model is described which predicts the plane-wave transmission characteristics for normal incidence. These elements are a new member of the group of arrays for which simple equivalent circuits are available.     

用于雷达T/R组件的SOI CMOS工艺射频芯片

<正>南京电子器件研究所国博电子有限公司基于0.18 nm SOI CMOS工艺研制了多款用于相控阵雷达的射频芯片,包括1~1.7 GHz有源下混频器、0.7~4 GHz有源下混频器、X波段6位移相器和X波段5位衰减器,芯片照片见图1。下混频器集成了射频、本振放大器,混频器以及中频放大器;X波段移相器和衰减器均集成了驱动器和ESD保护电路。该系列芯片解决了高集成度、小尺寸以及低功耗雷达T/R组件的关键问题。     

Equivalent circuit model of quantum-well lasers

A study of equivalent circuit model of quantum well lasers derived from quantum well rate equation has been carried out. Pulse response simulation results obtained from a SPICE simulator indicates that various modulation properties, e.g., turn-on delay, relaxation oscillation frequency, and on/off aspect ratio, have a substantially different behavior than those of DH lasers. This model offers a fundamental building block for the simulation of the over all signal transmission when using quantum-well lasers as a light source     

A circuit model of a system of VLSI interconnects for time responsecomputation

A novel computational model based on the spectral-domain approach for the characterization of a dispersive multiconductor system is developed for time response computation. The model consists of two identical impedance networks and equivalent voltage-controlled voltage sources, and it is particularly suitable for timing analysis. Since the model is constructed based on full-wave analysis, the hybrid nature of the VLSI interconnects is taken care of, and thus the model is valid at high frequencies when the longitudinal field components are no longer negligible. Signal distortions due to the dispersive nature of a multiconductor system are demonstrated by an example     

Scalable Compact Circuit Model for Differential Spiral Transformers in CMOS RFICs

A new compact circuit model for differential spiral transformers in CMOS radio frequency integrated circuits (RFICs) is developed in this paper. The model consists of two coupled “$hbox2-pi$” subcircuits for each inductor coil in the transformer. All the values of the circuit elements can be analytically calculated according to the process parameters and the device's geometric dimensions, making the model highly scalable and predictive. The model has very good accuracy as validated by comparison to a 2.5-dimensional full-wave numerical electromagnetic field solver.     

A CMOS model for computer-aided circuit analysis and design

An equivalent circuit model to simulate the current-voltage behavior of CMOS transistors is discussed. This model can simulate the full range of complementary MOSFET operation and can handle latchup at the circuit analysis level. Using effective injection efficiencies a switching criterion and a method of solution for a four parasitic bipolar transistor system have been developed and incorporated. The configuration of the CMOS device is computed from data submitted by the user. This includes well depth, MOSFET separation, doping levels, minority-carrier lifetime, substrate bypass resistors, the option to float either or both substrates, and bias conditions. The model can be used alone or incorporated into existing computer-aided-design programs for analysis of circuits which contain CMOS components     

Characterization,design and modeling of on-chip interleaved transformers in CMOS RFICs

This paper discusses the impacts of key geometrical parameters on the performance of interleaved transformers in CMOS radio frequency integrated circuits (RFICs). It also presents a compact circuit model for the transformer based on the “2-π” model of on-chip spiral inductors. All the RLC circuit elements can be calculated from the transformer’s geometrical and process parameters. Verification with accurately calibrated electromagnetic (EM) simulation data demonstrates accurate performance prediction and good scalability for a wide range of transformers’ layout.     

A novel bidirectional CMOS transceiver for chip-to-chip optical interconnects

A novel bidirectional complementary metal-oxide-semiconductor (CMOS) transceiver for chip-to-chip optical interconnects operating at 2.5 Gb/s is proposed, which shares the common block of a receiver and a transmitter on a single chip. The share of the common block of two circuits makes it possible to save 55% or 20% of power dissipation, depending on the operating mode. The chip in 0.18-/spl mu/m CMOS technology occupies an area of 0.82/spl times/0.82 mm/sup 2/, 70% of the total area of a typical unshared transceiver chip. The transmitting and receiving modes of operation show -3-dB bandwidths of 2.2 and 2.4 GHz and electrical isolations of -28 and -40 dB, respectively.     

An experimental study of scalability in shield-based on-wafer CMOS test fixtures

In this paper, the possibilities of employing full scalability to on-wafer complementary metal-oxide-semiconductor (CMOS) test fixtures is studied experimentally. Several test fixtures and in-fixture sets were fabricated and measured in order to find the significant parasitic components in shield-based fixtures. An improved method for applying bi-directional scaling to on-wafer shield-based test fixtures is proposed. This method takes into account the parasitic series resistance, series inductance, and parallel capacitance that are present in the test fixture. The proposed method can be used successfully in commonly known deembedding methods. This is verified through measurements. The test fixtures were fabricated on top of a lossy substrate using double-poly, three-metal-layer 0.35-/spl mu/m CMOS technology.     

Scalable compact circuit model and synthesis for RF CMOS spiral inductors

A scalable industry-oriented, 24-element "2-/spl pi/" compact circuit model for on-chip RF CMOS spiral inductors is presented. It has a good accuracy up to self-resonant frequency (SRF). Two levels of modeling approaches are provided, which are: 1) the fixed model, which extracts the values of circuit elements directly from the measured S-parameters of a given device, achieving high accuracy, but no scalability and 2) the scalable model, in which circuit elements are related to the geometry (i.e., layout) through a set of formulas with model parameters calibrated upon a few testing devices. The synthesis procedure is also discussed, which includes the scalable model and a SPICE simulator as the evaluation method within the iteration loop.     

A new compact model for monolithic transformers in silicon-based RFICs

A new compact model for monolithic transformers on silicon substrates is presented. The new lumped-element equivalent circuit model employs transformer loops to represent skin and proximity effects including eddy current loss in the windings of the transformer. In addition to the self-resistances and self-inductances of the windings, the effects of the frequency-dependent mutual resistance and mutual inductance are included in the model. The new compact model has been applied to a stacked transformer on a 10-/spl Omega//spl middot/cm CMOS substrate. The extracted circuit model shows very good agreement with data obtained by full-wave electromagnetic simulation and measurement over the frequency range of 0.1-10GHz.     

A new wideband compact model for spiral inductors in RFICs

A new wide-band compact model for planar spiral inductors on lossy silicon substrate is presented. Transformer loops are used in the series branch of the equivalent circuit model to include the effects of the frequency-dependent losses, in particular eddy-current loss in the silicon substrate. The new compact model and the standard 9-element model are extracted from measurement data of a typical 1.5-nH spiral fabricated on a low-resistivity CMOS substrate over a frequency range of 0.1 to 10 GHz. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new model are in excellent agreement with the measured results     

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.