A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power (LP) and a low noise figure (NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator (LO) signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demodulator is designed for an input radio frequency (RF) band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency (IF) band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain (VCG) ranging from 14.2 to 13.2 dB, and a minimum single-sideband NF (SSB-NF) of 9 dB. The measured third-order input intercept point (IIP₃) is -3.3 dBm for a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-nm LP CMOS technology, are also presented in this paper.     

45 GHz active HEMT mixer

A low-noise 45 GHz mixer has been realised using a high electron mobility transistor (HEMT). This is the first reported active mixer above 30 GHz and the first reported HEMT mixer. The mixer exhibits 1.5 dB maximum gain at 4 dBm local oscillator (LO) power and 8.1 dB noise figure, including a 2.6 dB NF IF amplifier, at 2 dBm LO power.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

26-34 GHz CMOS mixer

A 26-34 GHz fully integrated CMOS down mixer is presented. At 30 GHz RF frequency and 2.5 GHz IF frequency, 50 /spl Omega/ terminations, 5 dBm LO and 1.2 V/spl times/17 mA supply power, the circuit yields a conversion loss of 2.6 dB, an SSB NF of 13.5 dB and an IIP3 of 0.5 dBm.     

一种低噪声高线性度CMOS上变频混频器

设计实现了一种采用开关跨导型结构的低噪声高线性度上变频混频器,详细分析了电路的噪声特性和线性度等性能参数,本振频率为900 MHz。芯片采用0.18μm Mixed signal CMOS工艺实现。测试结果表明,混频器的转换增益约为8 dB,单边带噪声系数约为11 dB,输入参考三阶交调点(IIP3)约为10.5 dBm。芯片工作在1.8 V电源电压下,消耗的电流为10 mA,芯片总面积为0.63 mm×0.78 mm。     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

基于SiGe HBT工艺的GNSS接收机混频器设计

针对目前国内RFIC发展比较滞后的现状,设计了3款应用于GNSS接收机的基于0．5μm SiGe HBT工艺的混频器（Ⅰ、Ⅱ、Ⅲ）,并采用针对混频器的优良指数FOM（figure—of-merit）对这3个混频器进行结构和综合性能比较。3款混频器的供电电压为3-3V,本振LO输入功率为-10dBm,其消耗总电流、转换增益、噪声系数、1dB增益压缩点依次为：Ⅰ）8．7mA,15dB,4．1dB,-17dBm;Ⅱ）8．4mA,10dB,4．6dB,-10dBm;Ⅲ）5．4mA,11dB,4．9dB,-10dBm。而3款混频器的FOM分别为-57．8、-56．6、-54．3,表明混频器Ⅲ的综合性能最佳,混频器Ⅱ次之,最后为混频器Ⅰ。     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

基于CMOS工艺的改进型电流注入混频器

设计了一种改进型电流注入混频器.通过在吉尔伯特混频器电路的本振开关管源极引入电感形成谐振电路,消除了开关管源极寄生电容的影响,降低了混频器电路的闪烁噪声,增大了混频器电路的增益.混频器电路的设计采用SMIC 0.35 μm CMOS 工艺库,本振功率为-3 dBm.仿真结果表明,与改进前的混频器电路相比,当本振功率为-3 dBm时,改进型电流注入混频器电路的增益提高了1.76 dB,IIP3提高2.1 dBm,噪声系数降低了0.5 dB.     

Design and performance of low-current GaAs MMICs forL-band front-end applications

GaAs monolithic microwave integrated circuits (MMICs) with very low current and of very small size have been developed for L-band front-end applications. The MMICs fully employ lumped LC elements with uniplanar configurations. There are two kinds of MMICs: a low-noise amplifier and a mixer. The low-noise amplifier has a noise figure of 2.5 dB and a gain of 11.5 dB. The mixer has a conversion gain of 12.5 dB small local oscillator (LO) power of -3 dBm. Total current dissipation of the two MMICs is less than 8 mA with 3-V drain bias voltages     

A 77 GHz SiGe sub-harmonic balanced mixer

A novel SiGe 77 GHz sub-harmonic balanced mixer is presented with a goal to push the technology to its limit [SiGe2-RF transistor (f/sub T/=80 GHz)]. This new topology uses a compact input network not only to achieve high isolation between the LO and RF ports, but also to result in excellent 2LO-RF isolation. The measured results demonstrate a conversion gain of 0.7 dB at 77 GHz with an LO power of 10 dBm at 38 GHz, LO-RF isolation better than 30 dB, 2LO-RF isolation of 25 dB, and a P/sub 1dB/ of -8 dBm. The mixer core consumes 4.4 mA at 5 V. The circuit demonstrates that SiGe sub-harmonic mixers have comparable performance with GaAs designs, at a fraction of the cost.     

基于802.11a协议的无线局域网低噪声放大器和改进的有源双平衡混频器

提出了采用0.18μm CMOS工艺,应用于802.11a协议的无线局域网接受机的低噪声放大器和改进的有源双平衡混频器的一些简单设计概念。通过在5.8 GHz上采用1.8 V供电所得到的仿真结果,低噪声放大器转换电压增益,输入反射系数,输出反射系数以及噪声系数分别为14.8 dB,-20.8 dB,-23.1 dB和1.38 dB。其功率损耗为26.3 mW。设计版图面积为0.9 mm×0.67 mm。混频器的射频频率,本振频率和中频频率分别为5.8 GHz,4.6 GHz和1.2 GHz。在5.8 GHz上,混频器的传输增益,单边带噪声系数（SSB NF）,1 dB压缩点,输入3阶截点（IIP3）以及功率损耗分别为-2.4 dB,12.1 dB,3.68 dBm,12.78 dBm和22.3 mW。设计版图面积为1.4 mm×1.1 mm。     

Broadband single- and double-balanced resistive HEMT monolithicmixers

A double-balanced (DB) 3-18 GHz and a single-balanced (SB) 2-16 GHz resistive HEMT monolithic mixer have been successfully developed. The DB mixer consists of a AlGaAs/InGaAs HEMT quad, an active LO balun, and two passive baluns for RF and IF. At 16 dBm LO power, this mixer achieves the conversion losses of 7.5-9 dB for 4-13 GHz RF and 7.5-11 dB for 3-18 GHz RF. The SB mixer consists of a pair of AlGaAs/InGaAs HEMT's, an active LO balun, a passive IF balun and a passive RF power divider. At 16 dBm LO power, this mixer achieves the conversion losses of 8-10 dB for 4-15 GHz RF and 8-11 dB for 2-16 GHz RF. The simulated conversion losses of both mixers are very much in agreement with the measured results. Also, the DB mixer achieves a third-order input intercept (IP₃) of +19.5 to +27.5 dBm for a 7-18 GHz RF and 1 GHz IF at a LO drive of 16 dBm while the SB mixer achieves an input IP ₃ of +20 to +28.5 dBm for 2 to 16 GHz RF and 1 GHz IF at a 16 dBm LO power. The bandwidth of the RF and LO frequencies are approximately 6:1 for the DB mixer and 8:1 for the SB mixer. The DB mixer of this work is believed to be the first reported DB resistive HEMT MMIC mixer covering such a broad bandwidth     

60 GHz double-balanced up-conversion mixer on 130 nm CMOS technology

A millimetre-wave Gilbert-cell up-conversion mixer using standard 130 nm CMOS technology is presented. This mixer has a power conversion gain of better than 2 dB and has the highest reported OP 1 dB of -5.6 dBm when driven with a LO power of 0 dBm. The LO to RF isolation are better than 37 dB for LO from 57 to 65 GHz. Microstrip lines were employed for the matching network design at the mixer output. This is believed to be the first CMOS Gilbert-cell up-conversion mixer operating in the 60 GHz frequency band using fundamental LO.     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.     

A Low LO Power Mixer Utilizing the Body Effect

We propose a single-stacked CMOS mixer that can operate at low local oscillator (LO) power condition with a new switching mechanism. Gating the body terminal makes it possible for the mixer to operate in a more ideal switching mode by utilizing the body effect. Biasing at near pinch-off region gives rise to beneficial aspect, low power dissipation. This circuit is composed of all PMOS transistors which draw only 0.275 mA from a supply voltage of 1.8 V. This circuit features gain and noise enhancement characteristic, low power consumption, and simple topology. The proposed mixer achieves conversion gain of 18 dB, noise figure of 9.1 dB with 0 dBm LO power, and power consumption as low as 0.5 mW.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

一种新的射频CMOS混频器结构

提出了一种低电压高增益CMOS下变频混频器的新结构.这个结构避免了堆叠晶体管,因此可以在低电压下工作.在LO信号的频率为1.452GHz,RF信号频率为1.45GHz的情况下,仿真结果表明:混频器的增益为15dB,ⅡP3为-4.5dBm,NF为17dB,最大瞬态功耗为9.3mW,直流功耗为9.2mW.并对该混频器的噪声特性和线性度进行了分析.