Experimental comparisons in the electrical performance of long and ultrashort gate length GaAs MESFET's

Electrical properties of GaAs single-gate and dual-gate MESFET's with gate lengths of 1.2 µm and 0.2 µm have been compared. By reducing the gate length to 0.2 µm, a very high zero-gate-bias drain current Idssand a large increase in the pinchoff voltage were observed in both single-gate and dual-gate devices, Idssin the shorter gate FET was found to be very close to the full channel current. Only a slight improvement in the maximum intrinsic gmwas noted in the 0.2 µm FET's. The knee voltage for the zero-gate-bias curve was larger in the shorter gate FET. At low current levels, soft pinchoff and soft saturation behaviors were observed in the very short gate FET's. A striking feature of the GaAs MESFET is that its output conductance at large drain voltages does not degrade with shorter gate lengths.     

GaAs MESFET's fabricated on InP substrates

This paper reports the first successful MESFET fabrication in GaAs layers grown directly on InP substrates by molecular beam epitaxy (MBE). The fabricated GaAs MESFET's exhibit good I-V curves with complete pinch-off and saturation characteristics. About 100-mS/ mm transconductance was obtained for a 1.2-µm gate length device.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

X-Band Burnout Characteristics of GaAs MESFET's

X-band µs pulse, ms pulse, and CW-burnout data have been measured for two commercially available 1- µm gate GaAs MESFET's. Values of incident pulse power required to cause burnout indicate a threshold level for pulse durations 0.2 µs or longer and for CW. The incident power threshold level for burnout is in the range 3 to 6 W for the MESFET type with a Ti/Pt/Au gate metallization and in the range 1.5 to 3 W for the MESFET type with an Al gate metallization. Many MESFET's were observed to fail during a single pulse.     

Gigabit logic operation with enhancement-mode GaAs MESFET IC's

Enhancement-mode GaAs MESFET IC's have been fabricated using electron-beam lithography. A recessed-gate structure to reduce the gate-to-source resistance and an air-bridge overlay interconnect to reduce stray capacitance were employed. A 30-ps delay time with an associated power dissipation of 1.9 mW is obtained with a 0.6 × 20-µm gate GaAs MESFET, which is the highest speed among the GaAs FET logics. Divide-by-eight counter has exhibited a 3.8-GHz maximum clock frequency with a power dissipation of 1.2 mW/gate.     

A comparative analysis of GaAs and Si ion-implanted MESFET's

In this work, numerical calculations of device characteristics including theI-Vcharacteristic, small-signal parameters, and cutoff frequency are reported for silicon-implanted MESFET devices. The device dimensions and impurity profile are similar to those of GaAs MESFET's. Although Si MESFET devices have not found practical applications, these calculations provide a good comparison of the intrinsic frequency limits of GaAs and Si. Comparative analysis shows that there are differences in the magnitude of the small-signal parameters and channel current between GaAs and Si MESFET devices with the same geometries and implanted profiles. However, the general variations of small-signal parameters with respect to the drain voltage is similar for both materials. In addition, the calculations show that a 1-µm channel length GaAs MESFET device has a higher cut-off frequency by a factor of 1.8 than a similar Si MESFET. These results indicate that GaAs devices are intrinsically better suited for very high-speed switching devices.     

Physical basis of short-channel MESFET operation II: Transient behavior

The large-signal switching behavior of planar short-channel metal-semiconductor field-effect transistors (MESFET's) is simulated numerically. First, the intrinsic response of the MESFET is simulated in two space dimensions and time, using measured electric-field-dependent drift velocities and diffusivities in the conventional semiconductor equations; results of the intrinsic device simulations are then used to study the circuit behavior of Si and GaAs MESFET's in two-input NOR circuits. Although the simulated 1-µm-gate Si and GaAs MESFET's have intrinsic response times of 11 and 9 ps to a gate pulse of - 2 V, for fan-in and fan-out = 2, the Si and GaAs NOR gates have average gates delays of 318 and 118 ps, respectively, for 1-µm gate lengths. The power-delay products for these 1-µm-gate Si and GaAs circuits are 1.8 and 1.5 pJ, respectively. These results are compared with measured data and their physical basis is discussed.     

TOM3 capacitance model: linking large- and small-signal MESFETmodels in SPICE

Improved accuracy in the modeled gate capacitance of GaAs metal-semiconductor field-effect transistors (MESFET's) is obtained in SPICE using conservation of charge in an implanted layer. The gate junction creates a natural partition between mobile and fixed channel charges. Relating the gate charge to the channel current creates gate capacitances dependent upon the channel current derivatives linking the small-signal model to the large-signal equations. Results are illustrated using a depletion-mode MESFET     

I—V characteristics of GaAs MESFET with nonuniform doping profile

A simple analytical model of a GaAs MESFET with non-uniform doping is proposed. The analysis shows that at gate voltages well above the threshold (0.2-0.4 V) for a typical device the current saturation is related to the velocity saturation (with a possibility of a stationary domain formation at drain-to-source voltages high enough). Closer to the threshold the saturation is due to the channel pinchoff. In both regimes the nonuniformity of the doping profile may be essential. Another factor taken into consideration is the source series resistance which includes the contact resistance and the resistance of the gate-to-source region of the device. The calculated dependences of the transconductance and drain current on the gate voltage are in good agreement with the experimental results obtained by Eden, Zucca, Long, and others [1].     

Physics of short-gate GaAs MESFET's from hydrostatic pressure studies

The use of hydrostatic pressure to study the physics of a GaAs MESFET is reported for the first time. Two aspects of the physics of conventional 1-µm gate structures are focused upon: 1) the possible role played by hot-electron effects in the drain-current saturation and 2) the physical mechanism responsible for excess current. The pressure dependence of the low-field conductance, current-voltage characteristics, and VHF noise properties of the MESFET are examined and compared to those of a Gunn diode. The results show that hot-electron effects are similar in the two devices, thereby providing new evidence that current saturation is associated with Gunn domain formation. The results also suggest that the excess current at large gate voltages is due to electron injection into the substrate under the source side of the gate, rather than to other proposed mechanisms.     

Current-voltage characteristics, small-signal parameters, and switching times of GaAs FET's

A new two-dimensional model of a GaAs FET is proposed. The model takes into account diffusion processes and Gunn-domain formation under the gate but it requires a very small computer time. The electric-field profiles under the gate, current-voltage characteristics, the dependences of the transconductance and gate-to-source capacitance on the drain voltage, and the dependences of a characteristic switching time and power-delay product on the device thickness are calculated. The results of the calculation agree well with the experimental data found earlier by other authors. The proposed model can be used for a computer-aided design of GaAs FET amplifiers and logic elements and also for a comparative study of GaAs and InP MESFET's.     

Negative differential conductivity and isothermal drain breakdownof the GaAs MESFET

Electrical breakdown in GaAs MESFET's is simulated by two-dimensional (2-D) quasi hydrodynamic isothermal model with two types of carriers and “mixed” boundary conditions on the contacts-fixed drain current and fixed gate bias. It was demonstrated, that when some maximum drain voltage is reached the MESFET's differential conductivity becomes negative at every gate bias. The negative differential conductivity (NDC) is caused by the electric field reconstruction in the buffer by the injected carrier space charge. It is shown that the suggested breakdown model corresponds to the experimentally observed properties of the drain breakdown of the GaAs MESFET. The instantaneous burnout of the GaAs MESFET at the drain breakdown is explained by the uncontrollable drain current increase due to the NDC formation     

High-Speed and Low-Power GaAs Phase Frequency Comparator

A high-speed and low-power consumption phase frequency comparator (PFC) for a phase lock stable oscillator was designed and fabricated with a GaAs MESFET BFL circuit for the first time. The threshold voltage, gate width, and gate length of GaAs MESFET's in the PFC were determined by circuit simulations for a high-speed and low-power operation. The fabrication process used buried p-layer SAINT-FET's with 0.5-µm gate length. The fabricated PFC performed stable phase and frequency comparison up to 600 MHz at only 60 mW. Using dislocation-free wafers, the fabrication yield in the laboratory was more than 90 percent.     

Bias dependence of GaAs and InP MESFET parameters

A comparative analysis of the bias dependence of critical RF parameters in GaAs and InP metal-semiconductor field-effect transistors (MESFET's) led to the following conclusions. 1) The drain-gate feedback capacitance in GaAs MESFET's is lower than in InP MESFET's, because of a stronger tendency in GaAs to form stationary Gunn domains at the typical drain bias levels employed. 2) The drain-source output resistance in InP MESFET's is lower than in GaAs MESFET's mainly for high drain current units, a fact which is linked to a substrate related softer pinch-off behavior in InP. 3) The current-gain cutoff frequency fT, in the current saturation range of the GaAs MESFET decreases strongly with drain bias as a result of the formation of the stationary Gunn domain. In the InP MESFET, this effect is weaker. At the optimum bias, fT is only 10-20 percent higher in InP MESFET's than in GaAs ones.     

Improvement in threshold-voltage uniformity in submicrometer GaAs MESFET's using an implanted p layer

A significant improvement in threshold-voltage uniformity for submicrometer gate GaAs MESFET's fabricated by direct Si implan, tation was observed using an optimized p-buried layer on conventional undoped LEC-grown substrates. Using an optimized Be-implantation scheme, we have achieved standard deviations of the threshold voltage as low as 7.6 mV from 13 × 13 FET arrays and only 16.8 mV across a 3-in wafer for FET's with a gate length of 0.6 µm. This is a very promising result for extending the GaAs MESFET IC technology into VLSI circuit complexity.     

Determination of effective saturation velocity in n+self-aligned GaAs MESFET's with submicrometer gate lengths

The dependence of effective saturation velocity on gate length in n⁺self-aligned GaAs MESFET's with submicrometer gate lengths has been determined by comparing experimentalI-Vcharacteristics with that obtained from one-dimensional analysis and two-dimensional simulation. The experimentalI-Vcharacteristics have been precisely matched to the theoretical ones calculated by two-dimensional simulation with a quasi-static (effective) velocity-electric-field relationship and reasonable doping profiles. The effective saturation velocity determined by best fit is 2.3 × 10⁷cm/s, and is independent of the gate length in 0.3- to 1.0-µm range. Though this high value gives evidence of the velocity overshoot effects, the constant characteristic disagrees with the expectation of the simulations based on nonstationary electron transport. On the contrary, the saturation velocity determined by using one-dimensional analysis decreases with an increase in the gate length. This dependence is explained by taking into account the channel pinchoff mechanism for drain current saturation before velocity saturation.     

New Technology Towards GaAs LSI/VLSI for Computer Applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HFMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

TiW Silicide gate self-alignment technology for ultra-high-speed GaAs MESFET LSI/VLSI's

It has been found that TiW silicide film forms Schottky contacts on GaAs which are extremely stable even at temperatures of up to 850°C. Using this silicide for gate material, a novel self-alignment technique for GaAs MESFET's has been developed. A minimum propagation delay of 50 ps with 1.5-µ gate logic and successful fabrication of 1-kbit fixed address GaAs static memory cell arrays which are based on E/D type DCFL's indicate that TiW silicide gate self-alignment technology is a very promising candidate for achieving ultra-high-speed GaAs MESFET LSI/VLSI's.     

New technology towards GaAs LSI/VLSI for computer applications

For future large-scale computer applications, new device technologies towards GaAs LSI/VLSI have been developed: self-aligned fully implanted planar GaAs MESFET technology and high electron mobility transistor (HEMT) technology by molecular beam epitaxy (MBE). The self-aligned GaAs MESFET logic with 1.5-µm gate length exhibits a minimum switching time of 50 ps and the lowest power-delay product of 14.5 fJ at room temperature. The enhancement/depletion (E/D) type direct coupled HEMT logic has achieved a switching time of 17.1 ps with 1.7-µm gate length at liquid nitrogen temperature and more recently a switching time of 12.8 ps with 1.1-µm gate HEMT logic, which exceeds the top speed of Josephson Junction logic and shows the highest speed of any device logic ever reported. Optimized system performances are also projected to system delay of 200 ps at 10-kilogate integration with GaAs MESFET VLSI, and 100 ps at 100-kilogate with HEMT VLSI. These values of system delay correspond to the computer performance of over 100 million instructions per second (MIPS).     

Stability of performance and interfacial problems in GaAs MESFET's

Interface effects in GaAs MESFET's were investigated from the viewpoint of stability of performance. It was clarified, on the basis of a simple analytical model, that even a small fluctuation of the effective channel thickness due to interface effects causes drastic changes or drifts in performance characteristics of a GaAs MESFET. Paying attention mainly to the behavior of drain current, the interface effects were experimentally investigated for VPE-gown 1-µm-gate GaAs MESFET's with and without a buffer layer. It was revealed that they are due to deep acceptors or hole traps, which exist at the interfaces and in the buffer layer and the semi-insulating substrate, and found that the long-term drift is attributed to Cr in the buffer layer as well as in the semi-insulating substrate.