(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High- $k$ MISFETs

We have proposed a (111)-faceted metal source and drain (S/D) with a metal gate and a high-k gate dielectric for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The metal S/D is formed by epitaxially grown nickel disilicide. N-type or p-type dopants are segregated in the atomically flat metal/Si interfaces that help to reduce the effective Schottky barrier height between the epitaxial metal and silicon. Therefore, a single type of metal S/D can work for both n-type and p-type MISFETs. The dopant segregation is realized by an ion implantation into the epitaxial silicides and a subsequent low-temperature annealing. Operations of 6-nm-long n-type and p-type silicon-on-insulator MISFETs that came with a fully silicided gate electrode and a high-k gate dielectric were experimentally demonstrated. The excellent short-channel effect immunity due to the trapezoidal channel was also verified by numerical simulation.     

La基高k栅介质的研究进展

SiO2作为栅介质已无法满足MOSFET器件高集成度的需求,高k栅介质材料成为当前研究的热点。综述了高k栅介质材料应当满足的各项性能指标和研究意义,总结了La基高k栅介质材料的最新研究进展,以及在改正自身缺点时使用的一些实验方法,指出了有可能成为下一代MOSFET栅介质的几种La基高k材料。La基高k材料的研究为替代SiO2的芯片制造工艺提供优异的候选材料及理论指导,这是一项当务之急且浩大的工程。     

High-k dielectrics based field plate edge termination engineering in 4H-SiC Schottky diode

This paper develops a deep insight into the behaviour of high-k dielectric-based field plate on Ni/4H-SiC Schottky diode. It tries to explain the mechanism by which high-k materials outperform silicon dioxide, when used under the field plate. Phenomena like modulation of field enhancement factor, reshaping of equipotential contours and expansion of depletion region while maintaining fixed depletion ratio (length/width = 2.3) helps to understand the electrical behaviour of high-k dielectric-based field plate. High-k materials relaxed the equipotential contours under the field plate edge which resulted in electric field reduction up to 88% and significant drop from 6.6 to 2.2 in field enhancement factor at device edges. The study considers the field plate of different dielectrics (SiO₂, Si₃N₄, Al₂0₃, HfO₂) and in each case, analytically explores the optimisation of field plate parameters (overlap length and dielectric thickness, dielectric constant). All the investigations have been done using numerical simulations on calibrated setup.     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

Electrical and material property enhancement in HfTaSiON-gated MOS devices by tuning Hf composition

High dielectric constant (high-k) materials, as a replacement for conventional gate dielectrics, have been proposed to overcome the problem of excessive gate leakage current. HfSiON is a potential high-k gate dielectric material, but the value of its dielectric constant is considered a little too low. In this work, we incorporate Ta into HfSiON to form a HfTaSiON gate dielectric. The influences of different Hf contents in HfTaSiON and various post deposition anneal (PDA) treatments were studied in detail. Experimental results show thatimprovements on the material and electrical properties of metal-oxide-semiconductor (MOS) devices such as crystallization temperature, interface quality between high-k dielectric/Si, hysteresis, stress-induced leakage current (SILC) and interface trap density (D_it) are achieved with incorporating a suitable amount of Hf in HfTaSiON high-k gate dielectric     

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45?nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I _on/I _off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO₂ (zirconium-di-oxide) is found out to be the best alternative for SiO₂ (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.     

On Oxygen Deficiency and Fast Transient Charge-Trapping Effects in High-k Dielectrics

This letter correlates fast transient charging (FTC) in high-k gate dielectrics to variations in its oxygen content. Analysis of electrical and physical data suggests that the observed enhancement of FTC may be caused by reduction of the oxygen content in the high-k film due to O scavenging process induced by the HfSi_x metal electrode. A hypothesis correlating O scavenging from the high-k dielectric to O vacancy formation, which contributes to FTC, is proposed     

高k材料用作纳米级MOS晶体管栅介质薄层(上)

随着45 nm和32 nm技术节点的来临,传统的SiO2作为栅介质薄膜材料的厚度需缩小到1 nm之下,材料的绝缘性、可靠性等受到了极大的挑战,已不能满足技术发展的要求.高k材料成为代替SiO2作为栅介质薄层材料的不错选择,但是大多数高k材料是离子金属氧化物,其基本物理和材料特性导致产生很多不可靠因素.从高k材料的基本物理和材料特性角度,回顾了高k材料代替SiO2用作纳米级MOS晶体管栅介质薄层时产生的主要不可靠因素及根本原因.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

We have proposed a single metal/dual high-$k$ gate stack for aggressively scaled complementary metal–insulator–semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-$k$ dielectrics, such as MgO- and $hbox{Al}_{2}hbox{O}_{3}$ -containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.      

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

高k介质在浮栅型非挥发性存储器中的应用

随着微电子技术节点不断向前推进,基于传统浮栅结构的非挥发性存储器(NVM)技术遇到严重的技术难点,其中最主要的问题是SiO2隧穿层已经接近厚度极限,很难继续减薄.作为改进措施,引入高k介质作为新型隧穿层材料.文章介绍了高k材料的研究现状和在NVM器件中应用所取得的进展;最后,对高k介质进一步应用的研究趋势进行了展望.     

Electrical properties of Ta/sub 2/O/sub 5/ gate dielectric on strained-Si

High dielectric constant (high-k) thin Ta/sub 2/O/sub 5/ films have been deposited on tensilely strained silicon (strained-Si) layers using a microwave plasma enhanced chemical vapour deposition technique at a low temperature. The deposited Ta/sub 2/O/sub 5/ films show good electrical properties as gate dielectrics and are suitable for microelectronic applications. The feasibility of integration of strained-Si and high-k dielectrics has been demonstrated.     

A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric

An analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated.     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

A PNPN tunnel field-effect transistor with high-k gate and Iow-k fringe dielectrics

A PNPN tunnel field effect transistor(TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET’s performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.