Scaling I2L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I²L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I²L devices with geometries >1 µm is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I²L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

Subnanosecond self-aligned I2L/MTL circuits

A self-aligned I²L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aligned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-µm design rules and fabricated with this technology exhibit gate delays as small as 0.8 ns atI_{c} = 100µA for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

Complementary AlGaAs/GaAs HBT I2L (CHI2L)technology

The monolithic integration of non-self-aligned AlGaAs/GaAs N-p-n and P-n-p HBTs with selective organometallic vapor-phase epitaxy (OMVPE) has been utilized to demonstrate a low-power high-speed integrated injection logic (I²L) technology. Seventeen-stage ring oscillators with a logic swing of 0.7 V exhibited a delay of 65 ps per gate with power dissipation of 13 mW per gate for a speed-power product of 850 fJ. This value was in excellent agreement with SPICE simulations based on extracted device parameters which predicted a speed-power product of 840 fJ. Additional simulations predicated a 28-fJ speed-power product and more than a factor of 2 reduction in gate delay with improved epitaxial design and use of submicrometer emitters and self-aligned processing     

A mixed EFL I2L digital telecommunication integrated circuit

A bipolar digital telecommunications circuit has been designed in the OXIL technology as part of a VLSI upgrade of an existing digital switching circuit. The chip is unique in its exploitation of the OXIL oxide isolated process which allows both high gain "up" and "down" devices used for I²L and EFL (emitter function logic), respectively. This allowed the circuit designers to tailor power consumption, circuit speed, and gate density as needed. In particular, the high speed properties of EFL were utilized in the control section to provide accurate timing signals and satisfy tight propagation delay requirements in the register section. I²L, because of its greater density and low power, was used in the gate intensive register sections. Another novel feature of this device was the treatment of bus lines (up to 250 fanout) such as clock, clear, etc., in the I²L sections. The common multiline I²L drive problem has been overcome here by using high drive translators from EFL circuitry and a single pullup resistor per bus line to provide switched currents to all gates on that line.     

Poly I2L with deposited polysilicon collector

A new high speed high density poly I²L structure with deposited polysilicon collector is analyzed and modeled. The switching speed of the proposed poly I²L structure is 4 times higher than that of the conventional structures and the packing density is improved by a factor of 2.The proposed poly I²L structure is gnvestigated using a developed computer simulation model. Parameters sensitivity analysis of the structure is given. The minimum gate delay decreases as the intrinsic base sheet resistivity is increased and as the thin epitaxial layer under the base is decreased. Down scaling effects are discussed. It is shown that a lateral shift of PDP curves along the current axis is proportional to the change in the device area and the IR drop in npn base is proportional to the scaling factor.A structure with technology linewidth L = 2.5 μm exhibits minimum gate delay of 0.6 ns at 150 μA for fan-out F = 3, and a power-delay product of 30 fJ at low current levels. Simulation results are compared with experimental measurements performed on a given poly I²L structure and good agreement has been observed.     

Characteristics of I2L at low current levels

The validity of the injection model is assessed in the low power range. Experimental evidence is given that the three base current components (I_{nc}, I_{no}, and Ip) can be determined from a three-gate experiment. The results are explained from the underlying device physics. Experimental data are presented for the temperature dependence of the upward current gain.     

Laser recrystallized polysilicon for high performance I2L

A key process innovation that has the potential to make very significant improvements in the performance of (integrated injection logic) I²L is proposed and demonstrated. The process is based on replacing the p⁺extrinsic base-n^-substrate parasitic diode with an oxide capacitor, This would eliminate injection current losses to the underlying substrate, thus improving the current gain, the minimum propagation delay time, and the speed-power product of the structure. A buried oxide I²L structure of this type may be realized via the use of pulsed or CW laser recrystallization of polysilicon. An interesting feature of the proposed method is that the crystal material over SiO2would not be used for the active transistor area, thus relaxing the stringent material requirements of bipolar devices. The polysilicon may be deposited on a p⁺base patterned thermal oxide by LPCVD or by deposition in a high temperature epitaxial reactor. The realization of such structures is demonstrated here specifically for the case of pulsed laser annealing of polysilicon deposited by either of the above mentioned ways.     

Application of MoSi2to the double-level interconnections of I2L circuits

A new MoSi2-CVD-Al double-level interconnection system is developed to obtain a high packing density in I²L circuits. Taking advantage of MoSi2, a fine pattern consisting of a linewidth of 2.5 µm and a spacing of 1 µm is achieved for the first-level interconnections. This new system has a higher reliability than the normal Al-CVD-Al structure because of the stability of the MoSi2surface. The fundamental properties of I²L gates with MoSi2interconnections, namely, gain, propagation delay time, and toggle frequency of a T flip-flop, are measured. At practical injector currents, they show nearly the same values as with Al interconnections. The resistance effects of MoSi2interconnections are calculated with regard to the unbalance of the injector currents and increase of the propagation delay time. The calculations show that these effects can be ignored at an injector current of 1 µA/gate. At higher injector currents, the MoSi2interconnection resistance must be taken into account in I²L pattern layout.     

On the electrical properties of the I2L n-p-n transistor

The optimization of the I²L speed-power product requires a clear understanding of the physical mechanisms that control device performance. Test structures have been designed and fabricated to characterize both intrinsic and extrinsic elements of an I²L gate. The electrical properties of the intrinsic n-p-n transistor are compared to calculations. Good agreement between measured and calculated beta is obtained for both the up and down transistor without parametric fitting. Band shrinkage, degeneracy, and Auger recombination are found to be important factors in determining the n-p-n base current. Intrinsic up betas greater than 2000 have been measured. The importance of n-p-n beta on the unit cell effective beta and the gate switching time is discussed.     

The effects of phosphorus diffusion cooling rate on I2L gain

It has been found that the current gain of an I²L cell can be seriously degraded if the deep collector (phosphorus) diffusion is not slow cooled. A correlation between improper cooling rate and the generation of a severe edge dislocation network is established. This network is shown to result in leaky emitter-base and collector-base junctions in an I²L cell but not in a conventional n-p-n transistor. These leaky junctions correlate with the observed low gain. A model is proposed to explain the cooling rate dependence of the dislocation networks in terms of vacancy clustering.     

The dual origins of a bipolar breakthrough [I2L]

The author describes the independent discovery of integrated injection logic (I²L) in the early 1970s by researchers at IBM in West Germany and at Philips in the Netherlands. He examines the factors that motivated the work and contrasts the viewpoints and working methods of the two teams, the Germans proceeding along a logical path to a solution that revealed itself to the Dutch team in a flash of intuition     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

Efficient DC and AC analysis of I2L devices based on quasi-three-dimensional modeling

An efficient technique for the modeling of I²L devices is developed on the basis of quasi-three-dimensional (Q3D) models, where a device is represented by several one-dimensional model units and the network which combines them. This improved method is capable of treating both dc and ac characteristics within a reasonable computation time. The computed and experimental results are compared, and good agreement is obtained. The importance of high injection effects and lateral voltage drops is clarified for the βupfalloff of multicollector I²L devices at high current levels. The difference between downward and upward operation of the vertical transistor is pointed out. The possibility of applying this method to the optimization of device structure is also shown.     

An investigation of the intrinsic delay (speed limit) in MTL/I2L

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of today's MTL/I²L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

The effect of collector location on βuof I2L structures

I²L multicollector n-p-n transistor structures are used widely in LSI chips. Due to layout restrictions the collector could be at a distance from the injector. In this case, βuper collector is affected by the lateral voltage drop in the base. This effect becomes significant at higher current levels. In this work the lateral base region of the n-p-n transistor is modeled and a scheme is given to obtain the variation of βuwith the base current. The results are compared to measurements obtained using a three-collector structure.     

The effect of base resistance of the vertical npn transistor in I2L structures

Expressions are derived for the lateral base current and for the base-emitter voltage by solving the differential equations obtained from a physical model of the base region of the vertical npn transistor. The theoretical and experimental results concur in showing that on the one hand the decrease of the upward current gain of the individual collectors at higher values of the collector current is due to the lateral voltage drop, and that high injection effects appear only for small values of current gain which have no practical importance. On the other hand the curves of current gain plotted against collector current show that the lateral voltage drop causes a point of inflexion followed by a maximum. This effect is evident at that collector nearest to the injector (or even at several such collectors, depending upon how many there are). Furthermore it is seen that the decrease of the current gain is almost entirely independent of the current gain of the intrinsic transistor.     

10K Gate I2L and 1K component analog compatible bipolar VLSI technology—HIT-2

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10K I²L gates with 1K analog devices is proposed. The new technology, called high-density integration technology-2 (HIT-2), is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I²L active layer etching, and I²L current gain increase. I²L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BVCEOof more than 10 V and an fTof 5 GHz, and lateral p-n-p transistors having an fTof 150 MHz.     

Analysis of Si:Ge heterojunction integrated injection logic(I2L) structures using a stored charge model

A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I²L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I²L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I²L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NPN emitter layer. The inclusion of 16% Ge in the substrate-fed I²L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I²L even at a geometry of 3 μm. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure