用于超宽带接收机的高速低复杂度模拟自动增益控制环路

在射频接收机中,自动增益控制环路(AGC)根据接收信号幅度控制放大器增益,向后级模数转换器(ADC)提供恒定幅度的信号,以实现不同强度信号的正确接收。在超宽带(UWB)接收机中,极大的信号带宽给AGC的设计提出了挑战。本文提出了一个用于超宽带(UWB)接收机的模拟自动增益控制环路(AGC)。该AGC环路采用多级可变增益放大器(VGA)串联的放大器结构,通过峰值检测电路和模值运算电路检测输出复信号模值的峰值,和参考电位比较后反馈控制VGA的增益,从而得到恒定幅值的ADC的输入。整个电路结构简单,复杂度低。基于HJ0.18μmCMOS工艺的仿真结果表明,本文提出的AGC工作在500MHz带宽下,增益调节范围达40dB,三阶交调点为20dBm,能够满足UWB接收机的要求。     

Extending the bandwidth performance of heterojunction bipolartransistor-based distributed amplifiers

An InAlAs-InGaAs-InP HBT CPW distributed amplifier (DA) with a 2-30 GHz 1-dB bandwidth has been demonstrated which benchmarks the widest bandwidth reported for an HBT DA. The DA combines a 100 GHz fmax and 60 GHz fT HBT technology with a cascode coplanar waveguide DA topology to achieve this record bandwidth. The cascode gain cell offers 5-7 dB more available gain (MAG) than a common-emitter, and is used to extend the amplifier's upper frequency performance. A coplanar waveguide design environment is used to simplify the modeling and fabrication, as well as to reduce the size of the amplifier. Novel active load terminations for extending the DA's lower frequency response were separately demonstrated. The active loads are capable of extending the lower bandwidth performance by two decades resulting in performance below 45 MHz. This work explores both design techniques and technology capability which can be applied to other distributively matched HBT circuits such as active baluns for mixers, active combiners/dividers, and low DC power-broadband amplifiers     

Uniform Design of Multi-Peak Bandwidth Enhancement Technique for Multistage Amplifiers

A new technique for designing uniform multistage amplifiers (MAs) for high-frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. The intrinsic capacitances within transistors are exploited by the active negative feedbacks to expand the bandwidth. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Using the proposed topology, a six-stage amplifier in TSMC 0.35-mum CMOS process was designed. Measurement results show that the gain can be varied between 16 and 44 dB within 0.7-3.2-GHz bandwidth with less than 5.2-nV /radicHz noise. Die area of the amplifier is 175 mum times 300 mum.     

A new design topology for low-voltage CMOS current feedback amplifiers

A new topology for designing low-voltage current feedback amplifiers (CFAs) is presented. By employing a second-generation positive current conveyor followed by an operational amplifier in an unconventional manner, the design circumvents the problem of trying to achieve large transimpedance in a low-voltage environment. It is shown that this CFA configuration also results in near gain independent closed-loop bandwidth defined by a single feedback resistor. The proposed amplifier was verified experimentally by a chip designed using Taiwan Semiconductor Manufacturing Company's 0.18-/spl mu/m digital CMOS process of a single-ended power supply of 1.8 V.     

An 84 GHz Bandwidth and 20 dB Gain Broadband Amplifier in SiGe Bipolar Technology

This paper reports on the design, fabrication, and characterization of a lumped broadband amplifier in SiGe bipolar technology. The measured differential gain is 20 dB with a 3-dB bandwidth of more than 84 GHz, which is the highest bandwidth reported so far for broadband SiGe bipolar amplifiers. The resulting gain bandwidth product (GBW) is more than 840 GHz. The amplifier consumes a power of 990 mW at a supply of -5.5 V.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages

Using the concept of traveling-wave gain stages, novel GaAs pseudomorphic high electron-mobility transistor monolithic-microwave integrated-circuit (MMIC) distributed amplifiers (DAs) are demonstrated to achieve high gain and over several octaves of bandwidth performance simultaneously for microwave and millimeter-wave frequency applications. The cascaded single-stage distributed amplifier (CSSDA) is used as traveling-wave gain stages to improve the gain performance of the conventional distributed amplifier (CDA). By adopting the low-pass filter topology between the CDA and CSSDA and tuning the gain shape of CDA and CSSDA separately, a broad-band and high-gain DA, called CDA-CSSDA-2, was accomplished. The detailed design equations are derived for the broad-band matching design of this CDA-CSSDA-2. Two other MMICs, namely, a two-stage CSSDA called 2-CSSDA, and another two-stage design called CDA-CSSDA-1, are also included in this paper. This CDA-CSSDA-2 achieves 22/spl plusmn/1.5-dB small-signal gain from 0.1 to 40 GHz with a chip size of 1.5/spl times/2 mm/sup 2/. It also produces a gain-bandwidth product of 503 GHz, which is the highest among all reported GaAs-based DAs. The flat group delay also demonstrates the feasibility of this design for future digital optical communications and broad-band pulse applications.     

Design and performance of transferred electron amplifiers using distributed equalizer networks

This paper describes improved techniques for the design of broad-band linear reflection-type microwave amplifiers using transferred electron devices. These techniques have produced excellent agreement between amplifier design goals and performance. This agreement results from improvements in measuring techniques and data reduction in addition to the use of a distributed equalizer topology. Multistage amplifiers having a net gain of over 25 dB and a power output in excess of 0.4 W over a bandwidth of 4 GHz in X- band have been realized.     

3.1～5.2GHz超宽带可变增益低噪声放大器设计

低噪声放大器是超宽带接收机系统中最重要的模块之一,设计了一种可应用于3.1～5.2GHz频段超宽带可变增益低噪声放大器。电路输入级采用共栅结构实现超宽带输入匹配,并引入电流舵结构实现了放大器的可变增益。仿真基于TSMC 0.18μm RF CMOS工艺。结果表明,在全频段电路的最大功率增益为10.5dB,增益平坦度小于0.5dB,噪声系数小于5dB,输入反射系数低于-15dB,在1.8V电源电压下,功耗为9mW。因此,该电路能够在低功耗超宽带射频接收机系统中应用。     

Design and Performance of Monolithic GaAs Direct-Coupled Preamplifiers and Main Amplifiers

The design and performance of a GaAs direct-coupled preamplifier and main amplifier is described. The amplifiers are fabricated by the self-aligned implantation for n/sup +/ -Iayer technology (SAINT) process. The developed preamplifiers have 13-dB gain, 3-GHz bandwidth, and 4.8-dB noise figure for the one-stage amplifier, and 22-dB gain, 2.7-GHz bandwidth, and 5.6-dB noise figure for the two-stage amplifier. The developed four-stage main amplifier has 36-dB gain and 1.5-GHz bandwidth with a power consumption of 710 mW. These amplifiers are promising candidates for application to high-speed data communication systems.     

40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS

A novel circuit topology for high-gain distributed amplifiers is presented in this study. Based on the conventional distributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18-mum CMOS technology. The amplifier with a 3 times 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 times 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.     

Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers

In this paper, we present three MMIC low-noise amplifiers using dual-gate GaAs HEMT devices in a balanced amplifier configuration. The designs target three different frequency bands including 4-9 GHz, 9-20 GHz, and 20-40 GHz. These dual-gate balanced designs demonstrate the excellent qualities of balanced amplifiers in terms of stability and matched characteristics, while demonstrating higher bandwidth than designs with a single-stage common-source device. Additionally, noise performance is excellent, with the 4-9 GHz LNA demonstrating <1.75 dB noise figure (NF), the 9-20 GHz LNA <2.75 dB NF and the 20-40 GHz LNA <2.5 dB NF. Demonstrating high gain and excellent bandwidth, the dual-gate devices seem a logical choice for the balanced amplifier topology.     

Ultrahigh-efficiency power amplifier for space radar applications

This paper describes a broad-band switch mode power amplifier based on the indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The amplifier combines the alternative Class-E mode of operation with a harmonic termination technique that minimizes the insertion loss of matching circuitry to obtain ultrahigh-efficiency operation at X-band. For broad-band Class-E performance, the amplifiers output network employs a transmission line topology to achieve broad-band harmonic terminations while providing the optimal fundamental impedance to shape the output current and voltage waveforms of the device for maximum efficiency performance. As a result, 65% power-added efficiency (PAE) was achieved at 10 GHz. Over the frequency band of 9-11 GHz, the power amplifier achieved 49%-65% PAE, 18-22 dBm of output power, and 8-11 dB gain at 4 V supply. The reported power amplifier achieved what is believed to be the best PAE performance at 10 GHz and the widest bandwidth for a switch-mode design at X-band.     

0-40 GHz GaAs MESFET distributed baseband amplifier ICs forhigh-speed optical transmission

We describe distributed amplifiers built using advanced circuit design techniques to improve gain and noise performance at low frequencies. Using these techniques we have developed an amplifier IC with a 0-36 GHz bandwidth and a noise figure of 4 dB at low frequencies. This frequency range starting from 0 Hz makes it possible to use the IC as a baseband amplifier for SDH optical transmission systems and this noise figure is about 1 dB better than conventional distributed amplifiers. We also present another amplifier IC built using our loss compensation technique to improve high-frequency performance of the amplifier. This IC has a 0-44-GHz bandwidth, which is the widest among all reported GaAs MESFET baseband amplifiers     

Reduction of finite-gain effect in switched-capacitor filters

A simple technique for significantly reducing the effect of the finite gain of amplifiers on the performance of switched-capacitor filters is presented. The effectiveness of this technique has been established by extensive simulation studies. This technique has the potential for simplifying amplifier design and extending the frequency range of switched-capacitor filters by trading gain for bandwidth.     

Computer-Aided Design of Broad-Band and Low-Noise Microwave Amplifiers

We have found iterative optimization techniques to be very effective in the design of broad-band low-noise integrated amplifiers. This paper presents an objective function to maximize gain while minimizing ripple and noise figure. An optimization routine using this objective function is applied to the design of an L-band amplifier. The results of several runs using different objectives applied to the same circuit topology are presented to demonstrate both the flexibility of this technique and the tradeoffs involved. One of the designs was fabricated, and the measured and predicted performance agree closely over an octave bandwidth.     

Ka波段二次谐波回旋速调管放大器的PIC模拟

该文根据谐波回旋速调管放大器的注.波互作用特点,分析了放大器稳定工作的条件:对Ka波段二次谐波三腔回旋速调管放大器的注-波互作用进行了模拟计算,对放大器的注.波互作用电路参数进行了优化设计。模拟计算结果表明,在电子注电压为70kV,电子注电流15A,工作磁场为0.685T时,在35GHz频率放大器可以获得超过250kW的输出功率,大于21dB的增益,23%的效率和约为120MHz的带宽。计算结果为实际工程设计提供了有益的参考。     

Jitter considerations in the design of a 10-Gb/s automatic gain control amplifier

The effects of noise on random jitter in multistage broad-band amplifiers are analyzed. Limiting amplifiers are compared to automatic gain control (AGC) amplifiers with different gain profiles. Results are presented for a 10-Gb/s AGC amplifier implemented in an SiGe process with f_T of 45 GHz. Active peaking techniques were used to achieve a maximum gain of 48 dB with 7.8 GHz of bandwidth. The amplifier demonstrates low jitter and less than 0.5 dB of peak-to-peak output amplitude variation over a 50-dB input amplitude range. It consumes 30 mW of power from a 3.3-V supply. The amplifier core occupies 0.1 mm² and requires no external components     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices

This paper deals with the design of single-stage differential low-noise amplifiers for ultra-wideband (UWB) applications, comparing state-of-the-art planar bulk and silicon-on-insulator (SOI) FinFET CMOS technologies featuring 45-nm gate length. To ensure a broadband input impedance matching, the $g_{m}$-boosted topology has been chosen. Furthermore, the amplifiers have been designed to work over the whole UWB band (3.1–10.6 GHz), while driving a capacitive load, which is a realistic assumption for direct conversion receivers where the amplifier directly drives a mixer. The simulations (based on compact models obtained from preliminary measurements) highlight that, at the present stage of the technology development, the planar version of the circuit appears to outperform the FinFET one. The main reason is the superior cutoff frequency of planar devices in the inversion region, which allows the achievement of noise figure and voltage gain comparable to the FinFET counterpart, with a smaller power consumption.