Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

High-voltage lateral RESURF MOSFETs on 4H-SiC

High-voltage lateral RESURF MOSFETs have been fabricated on 4H-SiC with both nitrogen and phosphorus as source/drain and RESURF region implants. Blocking voltages as high as 1200 V and specific on-resistances of 4 Ω cm² have been obtained, with the high on-resistance attributed to poor inversion layer mobility. Phosphorus is most appropriate for the source/drain implants due to low sheet resistance and contact resistance with low temperature anneals. However, poor activation of low dose phosphorus implants at 1200°C makes nitrogen the preferred choice for the RESURF region     

High channel mobility in inversion layers of 4H-SiC MOSFETs byutilizing (112¯0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112¯0) face: 17 times higher (95.9 cm²/Vs) than that on the conventional (0001) Si-face (5.59 cm²/Vs). A low threshold voltage of MOSFETs on the (112¯0) face indicates that the (112¯0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (μ_(11¯00)/μ₍₀₀₀₁₎=0.85) reflects the small anisotropy in bulk electron mobility     

Design criteria of high-Voltage lateral RESURF JFETs on 4H-SiC

Integrated power electronics on SiC have great potential in future power electronics applications. In this paper, a novel vertical channel lateral junction field-effect transistor structure with reduced surface electric field effect is proposed for the first time on 4 H-SiC to address existing challenges in lateral power devices on SiC. Based on an experimentally proven channel design, the detailed design procedure of such a device has been investigated. Design criteria to optimize device forward blocking as well as conduction characteristics are studied. Parameter tolerance and design windows are discussed considering practical issues in device fabrication. Designs that will lead to an optimized tradeoff between device breakdown voltage and specific on-resistance are shown. With an 8-/spl mu/m-long drift region, a 1535-V breakdown voltage and 3.24 m/spl Omega//spl middot/cm/sup 2/ specific on-resistance can be achieved. This represents a figure-of-merit of 737 MW/cm/sup 2/, about 100 times higher than that of the best normally off lateral power devices reported in the literature. The proposed device can be an attractive candidate for power integrated circuit on SiC.     

MOCVD growth of GaBN on 6H-SiC (0001) substrates

B_xGa_1−xN films were deposited on 6H-SiC (0001) substrates at 1000°C by low pressure MOVPE using diborane, trimethylgallium, and ammonia as precursors. The presence of boron was detected by Auger scanning microprobe, the shift of the (00.2) x-ray diffraction peak, and low-temperature photoluminescence. A single-phase B_xGa_1−xN alloy with x=1.5% was produced at the gas phase B/Ga ratio of 0.005. Phase separation into wurtzite BGaN and the B-rich phase occurred for a B/Ga ratio in the 0.01–0.2 range. Only BN was formed for B/Ga >0.2. The B-rich phase was identified as h-BN with sp² bonding based on the results of Fourier transform infrared spectroscopy. As the diborane flow exceeds the threshold concentration, the growth rate of BGaN decreases sharply, because the growth of GaN is poisoned by the formation of the slow growing BN phase. The bandedge emission of B_xGa_1−xN varies from 3.451 eV for x=0% with FWHM of 39.2 meV to 3.465 eV for x=1.5% with FWHM of 35.1 meV. The narrower FWHM indicates that the quality of GaN epilayer is improved with a small amount of boron incorporation. The PL linewidths become broader as more boron is introduced into the solid solution.     

Nickel Ohmic Contacts to N-Implanted (0001) 4H-SiC

Samples for transmission line model (TLM) and Hall measurements were fabricated on (0001) 4H-SiC implanted with nitrogen at 1 × 10¹⁸ cm⁻³, 4 × 10¹⁸ cm⁻³, 1 × 10¹⁹ cm⁻³, 4 × 10¹⁹ cm⁻³, and 1 × 10²⁰ cm⁻³. Following high-temperature activation, the activation percentage dropped from ~90% to ~20%, and the Hall mobility decreased from ~100 cm²/V · s to ~20 cm²/V · s as the implant concentration increased from 1 × 10¹⁸ cm⁻³ to 1 × 10²⁰ cm⁻³. The specific contact resistance as a function of Hall concentration is compared with published data for Ni contacts to epitaxial layers. The specific contact resistance as a function of activation temperature was also studied for two fixed implant concentrations of 5 × 10¹⁸ cm⁻³ and 1 × 10²⁰ cm⁻³.     

偏晶向(0001)Si-面衬底上4H-SiC的LPCVD外延生长

化学气相沉积(CVD)是微电子器件用SiC外延材料的主要生长技术.为了获得高质量的4H-SiC外延材料,在偏向<1120>方向8°的4H-SiC(0001)Si-面衬底上,利用台阶控制生长技术进行4H-SiC的同质外延生长.表面形貌是SiC外延材料质量好坏的一个重要参数,为此研究了表面形貌与工艺参数的关系,探讨了4H-SiC外延膜的表面缺陷形成原因.利用Raman散射技术研究了非均匀4H-SiC外延材料的多晶型现象.     

偏晶向(0001)Si-面衬底上4H-SiC的LPCVD外延生长

化学气相沉积（CVD）是微电子器件用SiC外延材料的主要生长技术. 为了获得高质量的4H-SiC外延材料，在偏向〈1120〉方向8. 的4H-SiC (0001) Si-面衬底上，利用台阶控制生长技术进行4H-SiC的同质外延生长. 表面形貌是SiC外延材料质量好坏的一个重要参数，为此研究了表面形貌与工艺参数的关系，探讨了4H-SiC外延膜的表面缺陷形成原因. 利用Raman散射技术研究了非均匀4H-SiC外延材料的多晶型现象.     

偏晶向(0001)Si-面衬底上4H-SiC的LPCVD外延生长

化学气相沉积(CVD)是微电子器件用SiC外延材料的主要生长技术.为了获得高质量的4H-SiC外延材料,在偏向<1120>方向8°的4H-SiC(0001)Si-面衬底上,利用台阶控制生长技术进行4H-SiC的同质外延生长.表面形貌是SiC外延材料质量好坏的一个重要参数,为此研究了表面形貌与工艺参数的关系,探讨了4H-SiC外延膜的表面缺陷形成原因.利用Raman散射技术研究了非均匀4H-SiC外延材料的多晶型现象.     

Novel abrasive-free planarization of 4H-SiC (0001) using catalyst

A new abrasive-free planarization method for silicon carbide (SiC) wafers was proposed using the catalytic nature of platinum (Pt). We named it catalyst-referred etching (CARE). The setup equipped with a polishing pad made of Pt is almost the same as the lapping setup. However, CARE chemically removes SiC with an etching agent activated by a catalyst in contrast to mechanical removal by the lapping process. Hydrofluoric acid which is well known as an etchant of silicon dioxide (SiO₂) that cannot etch SiC, was used as the source of the etching agent to SiC. The processed surfaces were observed by Nomarski differential interference contrast (NDIC) microscopy, atomic force microscopy (AFM), and optical interferometry. Those observations presented a marked reduction in surface roughness. Moreover, low-energy electron diffraction (LEED) images showed that a crystallographically well-ordered surface was realized.     

SiC单晶片C面固结磨料化学机械抛光的研究

本文研究了三种不同种类的磨料对SiC单晶片去除率的影响.最终选用金刚石磨料作为SiC单晶片的化学机械抛光磨料.结果表明:固结磨料CMP的材料去除率是游离磨料的3倍以上,固结磨料抛光垫,可大幅度提高材料去除效率.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

Microstructures of InN film on 4H-SiC (0001) substrate grown by RF-MBE

InN film was grown on 4H-SiC (0001) substrate by RF plasma-assisted molecular beam epitaxy (RF-MBE). Prior to the growth of InN film, an InN buffer layer with a thickness of ~ 5.5 nm was grown on the substrate. Surface morphology, microstructure and structural quality of InN film were investigated. Micro-structural defects, such as stacking faults and anti-phase domain in InN film were carefully investigated using transmission electron microscopy (TEM). The results show that a high density of line contrasts, parallel to the growth direction (c-axis), was clearly observed in the grown InN film. Dark field TEM images recorded with diffraction vectors g = 1120 and g = 0002 revealed that such line contrasts evolved from a coalescence of the adjacent misoriented islands during the initial stage of the InN nucleation on the substrate surface. This InN nucleation also led to a generation of anti-phase domains.     

SiC单晶片化学机械抛光工艺参数模型的研究

Firstly, this paper presents an orthogonal test of six factors and five levels, called the chemical mechanical polishing （CMP） process parameters experiment, for determining the best process parameters and ranking the influencing factors from primary to secondary. The three most important factors are the polishing pressure, the polishing liquid concentration and the relative velocity ratio of polishing disk to polishing carrier. Then, based on this analysis, the three factors and three levels of the quadratic orthogonal regression test are put forward. A math- ematical model impacting the surface roughness has also been set up. Finally, this work has achieved a polished wafer, whose material removal rate （MRR） is in the range of 70-90 nm/h and the surface roughness （Ra） is between 0.3 nm and 0.5 nm.     

3300V 4H-SiC MOSFET 设计与加工

成功设计并制造了击穿电压超过3300V 的4H-SiC MOSFET。通过数字仿真优化了漂移层和DMOSFET有源区参数。漂移层N型外延厚度为33微米并且掺杂浓度为2.5E15cm-3。器件采用浮空场限制环作为终端。当栅极电压为20V,漏极电压为2.5V时,漏极电流为5A。     

Excellent effects of hydrogen postoxidation annealing on inversionchannel mobility of 4H-SiC MOSFET fabricated on (112¯0) face

Effects of hydrogen postoxidation annealing (H₂ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112¯0) face have been investigated. As a result, an inversion channel mobility of 110 cm²/Vs was successfully achieved using H₂ POA at 800°C for 30 min. H₂ POA reduces the interface trap density by about one order of magnitude compared with that without H₂ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H₂ POA. In addition, 4H-SiC MOSFET with H₂ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm²/Vs     

Preparation of ultrasmooth and defect-free 4H-SiC(0001) surfaces by elastic emission machining

In this work, elastic emission machining (EEM), which is a precise surface-preparation technique using chemical reactions between the surfaces of work and fine powder particles, is applied to the flattening 4H-SiC (0001) surface. Prepared surfaces are observed and characterized by optical interferometry, atomic force microscopy (AFM), and low-energy electron diffraction (LEED). The obtained images show that the processed surface has atomic-level flatness, and the subsurface damage and surface scratches of the preprocessed surface are almost entirely removed.     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

DC and Transient Performance of 4H-SiC Double-Implant MOSFETs

SiC vertical MOSFETs were fabricated and characterized, achieving blocking voltages around 1 kV and specific on-resistances as low as $R_{{rm SP}, {rm ON}} = hbox{8.3} hbox{m}Omega cdot hbox{cm}^{2}$. DC and transient characteristics are shown. Room and elevated temperature (up to 200 $^{circ}hbox{C}$) 600V/5A inductive switching performance of the SiC MOSFETs are shown with turn-on and turn-off transients of approximately 20–40 ns.