Vg=Vd/2应力模式下宽度变窄对HALO-pMOSFETs退化的影响

讨论了最差应力模式下(Vg=Vd/2)宽沟和窄沟器件的退化特性.随着器件沟道宽度降低可以观察到宽度增强的器件退化.不同沟道宽度pMOSFETs的主要退化机制是界面态产生.沟道增强的器件退化是由于沟道宽度增强的碰撞电离率.通过分析电流拥挤效应,阈值电压随沟道宽度的变化,速度饱和区特征长度的变化和HALO结构串联阻抗这些可能原因,得出沟道宽度增强的热载流子退化是由宽度降低导致器件阈值电压和串联阻抗降低的共同作用引起的.     

ZnO缓冲层改善Rubrene/C70有机太阳能电池的性能

通过制备结构为ITO/ZnO/C₇₀ /Rubrene/MoO₃/Al 的有机太阳能电池(OSCs),研究了ZnO作为阴极 修饰层对Rubrene/C70有机太阳能电池性能的改善。同时通过 优化ZnO的厚度研究了ZnO的工作机理。 从实验结果可以看出,随着ZnO厚度的变化,器件的短路电流密度(J_sc)、开路电压(V_oc)、填充因子 (FF)、光电转换效率(PCE)和串联电阻(R_s)等性能参数呈现出了规律 性变化,当ZnO层厚度比较 薄时,器件PCE随着厚度的增加不断增大,当ZnO层厚度为53nm时,器件PCE达到最高为1.13%, 对应的J_sc、V_oc、FF分别为2.82mA·cm－2、0. 84V、45.86%,R_s为66.2Ω·cm²,当ZnO层厚度继续增 加时,器件PCE开始减小。对比没有ZnO阴极修饰层,器件最优时 的Jsc、V_oc、FF和PCE 分别提高了49%、17%,R_s降低了56%。     

WO3对Rubrene/C70有机太阳能电池性能的改善

研究了WO₃对Rubrene/C₇₀有机太阳能电池 (OSCs)性能的 改善,制备了结构为ITO/WO₃/Rubrene/C₇₀/BCP/Al的OSCs,其中WO₃插入在I TO和Rubrene中间作为阳极修饰层。通过优化WO₃的厚度,研究了WO₃对OSCs性能的改善及其作用机理。实验发现,器件的短路电流Jsc、开路电压V_oc、 填充因子(FF)、光电转换效率(PCE)和串联电阻Rs等性能参数随WO₃厚度的变化呈规律性变化;当 WO₃厚度小于80 nm时,器件PCE随着厚度的增加不断增大;当W O ₃厚大于80 nm时,器件PCE随着厚度的 增加不断减小;当WO₃厚度为80 nm 时,器件PCE达到最高为1.03%, 相应的J sc、V_oc、FF分别为2.81mA·cm－2、 0.83V、43.85%,Rs为45.3Ω·cm²,对比没有WO₃修饰层, 器件的J_sc、V_oc、FF和PCE分别提高了31%、137%、17%,Rs降低了33%。     

半开态直流应力作用下AlGaN/GaN高电子迁移率晶体管的失效机制分析

本文研究了半开态直流应力条件下,AlGaN/GaN高电子迁移率晶体管的退化机制。应力实验后,器件的阈值电压电压正漂,栅漏串联电阻增大。利用数据拟合发现,沟道电流的退化量与阈值电压及栅漏串联电阻的变化量之间有密切的关系。分析表明,阈值电压的退化是引起饱和区沟道电流下降的主要因素,对于线性区电流,在应力开始的初始阶段,栅漏串联电阻的增大导致线性区电流的退化,随后沟道电流退化主要由阈值电压的退化引起。分析表明,在半开态应力作用下,栅泄露电流及热电子效应使得电子进入AlGaN层,被缺陷俘获,进而导致沟道电流退化。其中反向栅泄露电流中的电子被栅电极下AlGaN层内的缺陷俘获,导致阈值电压正漂;而热电子效应则使得栅漏串联区电阻增大。     

有效跨导为1052 mS/mm的高性能InP基In0.52Al0.48As/In0.53Ga0.47As HEMTs

我们成功研制了栅长为0.15 μm、栅宽为2?50 μm、源漏间距为2 μm 的InP 基In_0.52Al_0.48As/In_0.53Ga_0.47As高电子迁移率器件。室温下,当器件V_DS为1.7 V,V_GS为0.1 V时,其有效跨导达到了1052 mS/mm。传输线方法(TLM)测试显示器件的接触电阻为0.032 Ω.mm,器件欧姆接触电阻率为1.03?10_-7Ω.cm_-2. 正是良好的欧姆接触及其短的源漏间距减小了源电阻,进而使得有效跨导比较大。器件还有比较好的射频特性：当V_DS＝1.5 V, V_GS ＝0.1 V 时,f_T和f_max分别为151 GHz,303 GHz。文章报道的HEMT器件非常适合毫米波段集成电路的研制。     

深亚微米抗辐照PDSOI nMOSFET的热载流子效应

基于中国科学院微电子研究所开发的0.35 μm SOI工艺,制备了深亚微米抗辐照PDSOI H型栅nMOSFET.选取不同沟道宽度进行加速应力实验.实验结果表明,热载流子效应使最大跨导变化最大,饱和电流变化最小,阈值电压变化居中.以饱和电流退化10%为失效判据,采用衬底/漏极电流比率模型,对器件热载流子寿命进行估计,发现同等沟道长度下,沟道越宽的器件,载流子寿命越短.     

具有低噪声及高线性度的高性能MOCVD-SiNx/AlN/GaN 毫米波MIS-HEMTs

文章在超薄势垒AlN/GaN异质结构上采用金属有机化学气相沉积（MOCVD）原位生长SiN_x栅介质,成功制备了高性能的SiN_x/AlN/GaN金属-绝缘体-半导体高电子迁移率晶体管（MIS-HEMTs）。深能级瞬态谱（DLTS）技术测试SiN_x/AlN的界面信息,显示其缺陷能级深度为0.236 eV,俘获截面为3.06×10^-19 cm^-2,提取的界面态密度为10¹⁰~10¹² cm^-2eV^-1,表明MOCVD原位生长的SiN_x可以有效降低界面态。同时器件表现出优越的直流、小信号和噪声性能。栅长为0.15 μm的器件在2 V的栅极电压（V_gs）下具有2.2 A/mm的最大饱和输出电流,峰值跨导为506 mS/mm,最大电流截止频率（f_T）和最大功率截止频率（f_MAX）分别达到了65 GHz和123 GHz,40 GHz下的最小噪声系数（NF_min）为1.07 dB,增益为 9.93 dB。V_ds = 6 V时对器件进行双音测试,器件的三阶交调输出功率（OIP3）为32.6 dBm,OIP3/P_dc达到11.2 dB。得益于高质量的SiN_x/AlN界面,SiN_x/AlN/GaN MIS-HEMT显示出了卓越的低噪声及高线性度,在毫米波领域具有一定的应用潜力。     

基于PIN结构的Rubrene/C70太阳能电池的性能研究

实验制备了ITO/V₂O₅/Rubrene/C₇₀:Rub rene/C₇₀/BCP/Al的PIN结构有机太阳能电池(OSC),其中 Rubrene、Rubrene:C₇₀和C₇₀分别作为P、I和N层。通过改变I层厚度,研究了I 层对OSC性能的影响及作用机理。实验显示,I层厚为5nm时器件的功率转换效率η达到最大值为1.580%,同时 获得了较大的短路电流密度Jsc为4.365mA· cm－2;相对PN结构器件,功率转化效率η短路电流密度Jsc和填充因子FF分别提 高了40.3%、29.7%和8.2%。我们认为,I层中激子分离效率的提高导 致了器件性能的改善。     

采用红外快速热退火的晶体管TED效应与沟道尺寸的关系研究

硼的瞬间增强扩散（transient enhanced diffusion, TED）导致MOS晶体管出现反短沟道效应,阈值电压异常升高,严重影响器件性能和良品率,不同的器件尺寸,阈值电压增量不同,为探究沟道内杂质离子分布情况和器件尺寸对TED效应的影响,在40 nm CMOS工艺平台下,对调阈值注入、低掺杂漏极（LDD）离子注入和碳离子协同注入工艺进行参数调整实验,测量不同工艺参数、不同尺寸的晶体管阈值电压,采用TCAD工具仿真沟道内硼离子和间隙原子的浓度分布。实验结果表明:沟道长度逐渐缩小,阈值电压先上升,在0.55 μm处达到最高后迅速下降,上升速率随着沟道宽度的减小而降低。当沟道长度不变时,阈值电压随沟道宽度一直下降,且下降得越来越快。间隙硅原子由LDD离子注入引入并向沟道扩散,而硼离子聚集在LDD-沟道边界位置,但是在LDD和沟道形成的角落会向浅沟槽隔离（STI）区域泄漏,聚集和泄漏作用共同控制沟道内硼离子的浓度分布。TED效应导致的阈值电压漂移是受器件尺寸调控的,另外,高能量的碳协同注入结合红外快速热退火技术可以有效地抑制TED效应。     

注氧SOI上制作的CMOS器件的总剂量特性分析

研究了用注入掩埋氧化物的绝缘体上的硅(SOI)作衬底、并经不同的注入后退火处理而制作的CMOS器件的总剂量特性。所测量到的正面沟道SOI/CMOS器件的阈值电压漂移、亚阈值电压斜率衰减和迁移率衰减情况,与采用相同办法制作的体器件的这些参数的变化情况是一样的。 只要不影响正沟道晶体管性能,加负衬偏可降低背面沟道的阈值电压漂移。在目前采用的工艺条件下,正沟道器件的辐照性能与注入氧后的退火温度无关。辐照时,在硅/隐埋氧化物界面上氧的沉积会促进背沟器件界面态的产生。     

Junction parameters for silicon devices characterization

An innovative method for device characterization is developed to qualify microelectronic devices. The method is based on parameter extraction from the junction I–V characteristics. Their evolution during electrical aging and ionizing radiation experiments allows an evaluation of the magnitude of the degradation. Results obtained with commercial samples show a signature of both manufacturer and technological processes. This method is easy to implement in a control process for device characterization.     

A power SIPOS MISS device

Power metal-insulator-silicon-switch (MISS) devices fabricated using semi-insulating polysilicon (SIPOS) for the insulator layer are discussed. The SIPOS MISS devices have an active area of 4.5 mm² and can carry in excess of 8 A. The typical switching voltage of these devices is 20 to 25 V with a negative temperature coefficient. They have a typical switching time of 200 ns and a very fast turn-off time. No degradation in device performance is observed after high current pulsing. Power SIPOS MISS devices offer an alternative to conventional four-layer switching devices, yielding faster switching characteristics while maintaining process compatibility     

A thorough investigation of the degradation induced by hot-carrierinjection in deep submicron N- and P-channel partially and fullydepleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V _d=V_t,V_d/2 or V_d) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO₂ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress     

Optimization of LDD devices for cryogenic operation

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K     

Optimizing the hot carrier reliability of N-LDMOS transistor arrays

Smart power management applications often require operation in the 20–30 V range. These applications combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current density and minimal on-resistance (R_dson), LDMOS devices are implemented in transistor arrays. Because of the high voltages and currents applied to these devices hot carrier degradation is a real reliability concern. This paper discusses several aspects of N-LDMOS hot carrier reliability including measurement techniques, degradation mechanism, and the effect of both one-dimensional (1-D) and two-dimensional (2-D) layout effects on the hot carrier degradation behavior of these devices. This paper focuses on device layout optimization rather than process changes since layout optimization has the advantage of improving performance without impacting other supported devices.     

Suppressing Ion Migration across Perovskite Grain Boundaries by Polymer Additives

Passivation of organometal halide perovskites with polar molecules has been recently demonstrated to improve the photovoltaic device efficiency and stability. However, the mechanism is still elusive. Here, it is found that both polymers with large and small dipole moment of 3.7 D and 0.6 D have negligible defect passivation effect on the MAPbI₃ perovskite films as evidenced by photothermal deflection spectroscopy. The photovoltaic devices with and without the polymer additives also have comparable power conversion efficiencies around 19%. However, devices with the additives have noticeable improvement in stability under continuous light irradiation. It is found that although the initial mobile ion concentrations are comparable in both devices with and without the additives, the additives can strongly suppress the ion migration during the device operation. This contributes to the significantly enhanced electrical-field stress tolerance of the perovskite solar cells (PVSCs). The PVSCs with polymer additives can operate up to −2 V reverse voltage bias which is much larger than the breakdown voltage of −0.5 V that has been commonly observed. This study provides insight into the role of additives in perovskites and the corresponding device degradation mechanism.     

Effects of two-step high temperature deuterium anneals on SONOSnonvolatile memory devices

The deterioration of the Si-SiO₂ interface is associated with the degradation of long-term retention in polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memory (NVSM) devices. Two-step high temperature deuterium anneals, applied in SONGS device fabrication for the first time, improves the endurance characteristics and retention reliability over traditional hydrogen anneals. Electrical characterization shows deuterium-annealed SONOS devices have nearly one order of magnitude longer retention time than hydrogen-annealed devices after 10⁷ erase/write cycles at 85°C to provide an extrapolated 0.5 V detection window at ten years     

The effect of gate metal interdiffusion on reliability performance in GaAs PHEMTs

While Ti metal interdiffusion of Ti-Pt-Au gate metal stacks in GaAs pseudomorphic HEMT (PHEMTs) has been explored, the effect of Ti metal interdiffusion on the reliability performance is still lacking. We use a scanning transmission electron microscopy technique to correlate Ti-metal-InGaAs-channel-separation and Ti-sinking-depth with a threshold voltage V/sub T/. It has been found that Ti-sinking-depth is insensitive to V/sub T/. However, Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus affecting the I/sub dss/ degradation rate. Accordingly, we observe the dependence of /spl Delta/I/sub dss/ on V/sub T/. Devices with less negative V/sub T/ exhibit inferior reliability performance to those devices with more negative V/sub T/. The results provide insight into a critical device parameter, V/sub T/, for optimizing reliability performance based on I/sub dss/ degradation.     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device