Analysis, design, and performance of micropower circuits for a capacitive pressure sensor IC

An integrated circuit has been designed, built, and testing as part of a capacitive pressure transducer. High-accuracy compact micropower circuits utilizing a standard bipolar IC process without any special components or trimming are used. The key circuits for achieving this performance are a Schmitt trigger oscillator and a bandgap voltage reference. The sensor circuits consume 200 /spl mu/W at 3.5 V, can resolve capacitance changes of 300 p.p.m., measure temperature to /spl plusmn/0.1/spl deg/C over a limited temperature range, and presently occupy 4 mm/SUP 2/ on a 2 mm/spl times/6 mm implantable monolithic silicon pressure sensor. Further scaling of the sensor is discussed showing that a reduction of area by a factor of 4 is achievable.     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

TFT-LCD驱动芯片的二级驱动电路

针对单芯片集成的TFT-LCD驱动芯片的特性,提出了在γ校正电路中加入两级驱动Buffef的驱动电路结构,以及提高其驱动能力的有效措施.对于具有13个驱动buffer的二级驱动电路,当由一个灰度电压驱动全部396个像素单元时,驱动电压的最大安定时间约为19.2μs;静态消耗电流为518μA,与传统的64个驱动buffer电路相比,其功耗减小了77%.本文的设计结果已成功应用于132RGB×176分辨率、26万色彩色显示手机用TFT-LCD驱动芯片中,其也可用于PDA、数码相机等其他便携电子设备的显示驱动.     

Abrupt power-off detector for mobile TFT-LCD driver IC using dual power supply

A circuit technique to detect unexpected power conditions such as battery separation is presented. Abrupt power-off owing to unexpected power conditions may cause an abnormal display in mobile TFT-LCDs because an adequate power-off sequence cannot be performed. The proposed abrupt power-off detector (APD) recognises decay of supply voltage and generates a signal to perform a proper power-off sequence. As mobile TFT-LCD driver ICs are usually operated with dual power supply, the APD detects abrupt power-off for both of the power supplies. To demonstrate the feasibility of the APD, a test chip was designed and fabricated in a 30 V/4 /spl mu/m 5 V/0.8 /spl mu/m 2.5 V/0.25 /spl mu/m triple-well CMOS process. Experimental results show that the proposed APD improves display quality by allowing a proper power-off sequence at all abrupt power-off conditions.     

A 1.1-V 270-/spl mu/A mixed-signal hearing aid chip

This paper presents a single-chip mixed-signal IC for a hearing aid system. The IC consumes 270 /spl mu/A of supply current at a 1.1-V battery voltage. The presented circuit and architectural design techniques reduce the total IC power to 297 /spl mu/W, a level where up to 70 days of lifetime is achieved at 10 h/day for a small zinc-air battery. The measured input referred noise for the entire channel is 2.8 /spl mu/Vrms and the average THD in the nominal operating region is 0.02%. The jitter for the on-board ring oscillator is 147 ps rms. The chip area is 12 mm/sup 2/ in a 0.6-/spl mu/m 3.3-V mixed-signal CMOS process.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

An analog front end for 2400-bit/s split-band full-duplex modems

An analog front-end LSI for 1200/2400 full-duplex modems which conform to CCITT V.22. and Bell 212A is described. The chip includes A/D and D/A converters, bandlimiting filters, delay equalizers, AGC circuit, tone generator, multipurpose low-pass filter, and voltage reference generator. The chip is fabricated by a 5-/spl mu/m CMOS process, and chip size is 6.50 mm/spl times/6.37 mm. The circuit operates from +5.0-V and -5.0-V power supplies. Typical power consumption is 100 mW.     

Practical charge-transfer amplifier design architectures for low-power flash A/D converters

Two improved charge-transfer amplifiers (CTAs), used as zero-static-bias comparator preamplifiers in flash analog-digital converters, are proposed. The first improvement eliminates the capacitive coupling at the amplifier input, reducing area and input capacitance. The second eliminates the need for a common-mode output reference voltage by deriving the common-mode output from a switched average of the power supplies. In the latter, nearly a full-scale input range is achieved while preserving the low-power low offset characteristics of earlier CTAs. Voltage comparator devices were constructed in 0.6-/spl mu/m double-poly, triple-metal CMOS to test the prototype CTA architectures. Input common-mode range and offset performance consistent with simulation data is demonstrated with a 10X reduction in input capacitance. Measured dynamic power dissipation on the order of 3-6 /spl mu/W/MSPS is observed. The experimental CTA preamplifiers occupy roughly 0.015 mm/sup 2/.     

CMOS micro-power output stage for integrated voltage references

A CMOS micro-power, class-AB output stage with high current-drive capability for integrated voltage references is presented. A weak-inversion MOS translinear-loop ensures that the harmonic mean of the push and pull currents equals a constant bias current. It can source/sink 20 mA with only 15 /spl mu/A quiescent current, thus achieving very high power efficiency. It operates from a 2.5 V power supply and is stable for capacitive loads up to 2 nF.     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

A frequency compensation scheme for LDO voltage regulators

A stable low dropout (LDO) voltage regulator topology for low equivalent series resistance (ESR) capacitive loads is presented. The proposed scheme generates a zero internally instead of relying on the zero generated by the load capacitor and its ESR combination for stability. It is demonstrated that this scheme realizes robust frequency compensation, facilitates the use of multilayer ceramic capacitors for the load of LDO regulators, and improves transient response and noise performance. Test results from a prototype fabricated in AMI 0.5-/spl mu/m CMOS technology provide the most important parameters of the regulator viz., ground current, load regulation, line regulation, output noise, and start-up time.     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.     

Micropower high-performance SC building block for integrated low-level signal processing

A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.     

Opportunistic multichannel driving scheme for low power mobile TFT-LCD driver IC

A novel source driving scheme called opportunistic multichannel driving (OMCD) is proposed for use in mobile TFT-LCD driver ICs (T-LDIs). In the OMCD scheme, the operation of the source drivers of a T-LDI is controlled by the equivalence of RGB colour data for adjacent pixels. That is, one source driver drives the neighbouring source lines as well as the corresponding one when the colour data of adjacent pixcels are identical to each other. With this scheme, all the source drivers associated with the neighbouring source lines can be completely turned off, allowing the reduction of static and dynamic current of these drivers. A test chip was fabricated in a 5 V/0.8 /spl mu/m 2.5 V/0.25 /spl mu/m triple-metal CMOS process, and the experimental result shows that the power reduction of 12-21% was obtained with die size overhead less than 0.5%.     

A high f/sub OSC//f/sub T/ ratio VCO in SiGe BiCMOS technology

A 37-GHz voltage controlled oscillator (VCO) fabricated in IBM's 47-GHz SiGe BiCMOS technology is presented. The VCO achieves a phase noise of -81dBc/Hz at 1-MHz offset from the carrier while delivering an output power of -30dBm to 50 /spl Omega/ buffers. Drawing 15-mA of dc current from a 3-V power supply the VCO occupies 350/spl mu/m/spl times/280/spl mu/m of silicon area. Capacitive emitter degeneration and compact layout are used to achieve high f/sub OSC//f/sub T/ ratio.     

A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm/spl times/20 mm/spl times/1.2 mm and the sensor area is 19.2 mm/spl times/15 mm. The size of the prototype cell is now 60 /spl mu/m/spl times/60 /spl mu/m at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-/spl mu/m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。