Lumped-circuit model extraction for vias in multilayer substrates

Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.     

A design-oriented methodology for accurate modeling of on-chip interconnects

An accurate modeling methodology for typical on-chip interconnects used in the design of high frequency digital, analog, and mixed signal systems is presented. The methodology includes the parameter extraction procedure, the equivalent circuit model selection, and mainly the determination of the minimum number of sections required in the equivalent circuit for accurate representing interconnects of certain lengths within specific frequency ranges while considering the frequency-dependent nature of the associated parameters. The modeling procedure is applied to interconnection lines up to 35 GHz obtaining good simulation-experiment correlations. In order to verify the accuracy of the obtained models in the design of integrated circuits (IC), several ring oscillators using interconnection lines with different lengths are designed and fabricated in Austriamicrosystems 0.35 μm CMOS process. The average error between the experimental and simulated operating frequency of the ring oscillators is reduced up to 2% when the interconnections are represented by the equivalent circuit model obtained by applying the proposed methodology.     

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-$mu$m CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.      

Scalable Approach for HBT's Base Resistance Calculation

This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBT's base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed.      

A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology

In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.      

Parameter extraction and electrical characterization of highdensity connector using time domain measurements

Two coupled connector pins can be represented by an equivalent circuit consisting of six parameters, namely, self capacitance/self inductance per pin, mutual capacitance between pins and mutual inductance between pins. A systematic parameter extraction algorithm has been discussed in this paper using time domain reflectometry (TDR) measurements. This method uses a combination of stand-alone, common mode, and differential mode measurements to extract the connector parasitics. The accuracy of the equivalent circuit has been studied in detail using crosstalk measurements     

基于K参数思想的快速三维互连电感电阻提取算法

在GHz以上高频集成电路中,电感寄生效应已严重影响了电路性能,必须研究有效的算法提取互连电感电阻.本文基于K参数(电感矩阵的逆)较好的局部化特性,提出适应高频情况的互连电感电阻提取算法.通过采用有效的窗口选择技术和导体细丝划分,以及在细丝电感计算复用和导纳矩阵求逆两方面的改进,本文算法可有效处理复杂的多层互连结构,在保持较好精度的情况下,计算速度比FastHenry快上百倍.     

IC中多余物缺陷对信号串扰的定量研究

该文研究了铜互连线中的多余物缺陷对两根相邻的互连线间信号的串扰,提出了互连线之间的多余物缺陷和互连线之间的互容、互感模型,用于定量的计算缺陷对串扰的影响。提出了把缺陷部分单独看作一段RLC电路模型,通过提出的模型研究了不同互连线参数条件下的信号串扰,主要研究了铜互连线的远端串扰和近端串扰,论文最后提出了一些改进串扰的建议。实验结果证明该文提出的信号串扰模型可用于实际的电路设计中,能够对设计人员设计满足串扰要求的电路提供指导。     

VLSI互连线频变K参数和频变电阻的有效提取算法

在GHz以上高频集成电路中,必须考虑互连线的电感寄生效应,以便对电路性能进行准确的分析和验证. K参数矩阵(部分电感矩阵的逆)由于其较好的局部化特性,被广泛接受并应用于对互连电感效应进行建模.但多数已有文献未考虑高频效应或效率不高.本文提出一种新的三维频变K 参数提取算法,通过与窗口技术相结合、以及窗口内线性方程组的有效求解,该算法具有较高的计算效率,同时,在此基础上,通过少量额外运算还可得出频变电阻.数值实验表明,该算法可处理复杂的互连结构,并且在保持较高准确度的情况下,其速度比电感提取软件FastHenry快几十至几百倍.     

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.     

FDTD modeling incorporating a two-port network for I/O line EMIfiltering design

Electromagnetic interference (EMI) filters are often utilized on I/O lines to reduce high-frequency noise from being conducted off the printed circuit board (PCB) and causing EMI problems. The filtering performance is often compromised at high frequencies due to parasitics associated with the filter itself, or the PCB layout and interconnects. Finite difference time domain (FDTD) modeling can be used to quantify the effect of PCB layout and interconnects, as well as filter type, on the EMI performance of I/O line filtering. FDTD modeling of a T-type and π-type filter consisting of surface-mount ferrites and capacitors is considered herein. The FDTD method is applied to model PCB layout and interconnect features, as well as the lumped element components, including the nonlinear characteristics of ferrite surface-mount parts. The EMI filters with ferrites; are included in the modeling by incorporating the time-domain Y-parameters of the two-port network into the FDTD time-marching equations. Good agreement between the FDTD modeling and S-parameter measurements supports the new FDTD algorithm for incorporating two-port networks     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics     

A high-performance hybrid electrical-optical interconnectiontechnology for high-speed electronic systems

A new and innovative interconnection technology applicable for printed circuit boards is presented. This technology is widely compatible with the existing design and manufacturing processes and technologies for conventional multilayer pc boards and it combines electrical and optical interconnects on pc board level. It provides the potential for on-board bandwidth of several Gb/s and closes the bottleneck caused by the limited performance of electrical interconnection technology. After giving an overview on the most important basic technologies and first available results and engineering samples, the focus of this paper is on the development of appropriate modeling methodologies and simulation algorithms necessary for designing and optimizing optical on-board interconnects within the conventional electrical pc board environment     

Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

Modeling DC power-bus structures with vertical discontinuitiesusing a circuit extraction approach based on a mixed-potential integralequation

The DC power-bus is a critical aspect in high-speed digital circuit designs. A circuit extraction approach based on a mixed-potential integral equation is presented herein to model arbitrary multilayer power-bus structures with vertical discontinuities that include decoupling capacitor interconnects. Green's functions in a stratified medium are used and the problem is formulated using a mixed-potential integral equation approach. The final matrix equation is not solved, rather, an equivalent circuit model is extracted from the first-principles formulation. Agreement between modeling and measurements is good, and the utility of the approach is demonstrated for DC power-bus design     

An efficient crosstalk parameter extraction method for high-speedinterconnection lines

A proposal is presented for an effective extraction method for crosstalk model parameters of high-speed interconnection lines. In the extraction procedure, mutual capacitance and mutual inductance of the coupled interconnection lines are extracted based on S-parameter measurement, time-domain-reflectometry (TDR) measurement and subsequent microwave network analysis. The extraction method is useful for characterizing homogeneous guiding structures, where the propagation of coupled transverse electromagnetic (TEM) modes is supported. In contrast to previous extraction methods, the suggested procedure requires fewer on-wafer probing steps and does not need matched terminations in the test device for high-frequency probing. The extracted models can be readily used with simulation program with integrated circuit emphasis (SPICE) circuit simulation. The procedure can also be used for modeling the crosstalk in packaging structures and multichip modules (MCMs). The proposed procedure has been successfully applied to the crosstalk model extraction of on-chip interconnection lines. Crosstalk model parameters were obtained for different line structures, spaces, and widths. Finally, the validity and reliability of the extracted models were examined by comparing a SPICE circuit simulation using the extracted crosstalk model parameters with high-speed time-domain crosstalk measurement. A close agreement was observed in the amplitude and pulse shape between the simulation and the measurement, showing the accuracy and usefulness of the proposed extraction method     

Circuit models for three-dimensional geometries includingdielectrics

The partial element equivalent circuit (PEEC) approach has proved useful for modeling many different electromagnetic problems. The technique can be viewed as an approach for the electrical circuit modeling for arbitrary 3-D geometries. Recently, the authors extended the method to include retardation with the rPEEC models. So far the dielectrics have been taken into account only in an approximate way. In this work, they generalize the technique to include arbitrary homogeneous dielectric regions. The new circuit models are applied in the frequency as well as the time domain. The time solution allows the modeling of VLSI systems which involve interconnects as well as nonlinear transistor circuits     

片上螺旋变压器等效电路参数的直接提取

本文比较了四端口和两端口测试方式下变压器模型的差异。虽然两端口测试方式对变压器的测试和应用更为合适,但它将给模型参数的提取带来巨大困难。在这篇文章中,一种基于物理意义的等效电路模型和它相应的直接提取步骤被提出来用于片上变压器。基于两端口（而非四端口）测试方式,这种参数提取步骤能够提取器件的模型参数而不需要使用任何参数优化和拟合。在这个步骤中,一个新方法首次被提出用来提取阶梯电路的参数,而阶梯电路被广泛用于模拟各种无源器件中的趋肤效应。这样,这个方法便可以推广应用到其他无源器件的建模中,如片上传输线、电感、巴伦等。为了检验这种参数提取步骤的有效性和准确性,我们用90-nm 1P9M CMOS工艺制作了一个片上互绕型变压器。我们比较了模型仿真和实际测试在自感、品质因数、感性互感系数和阻性互感系数等方面的结果,在很宽的频带宽度内这两者吻合得很好。     

Thermal-Mechanical Process Simulation of an Advanced NCF Technology

The paper introduces an advanced nonconductive film (NCF) typed FC technology employing a novel compliant composite interconnect structure. The interconnect reliability and bondability of the technology are demonstrated through experimental thermal humidity (TH) test in conjunction with a two-point daisy chain resistance measurement. The alternative goal of the study aims to look into the insight of the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. For effectively simulating the bonding process, a process-dependent finite-element (FE) simulation methodology is performed. The validity of the proposed methodology is verified through several experimental methods, including a Twyman-Green (T/G) interferometry technique for warpage measurement, and a four-point probe method for contact resistance measurement. At last, a design guideline for improved process-induced thermal-mechanical behaviors is presented through parametric FE analysis. Both numerical and experimental results demonstrate the feasibility in applying the novel compliant interconnects to achieve a proper contact stress at various temperature environments so as to hold a low and stable connection resistance at elevated temperature. Most importantly, the novel interconnects survive the 85degC/85%RH TH test for 500 hours.     

A New Analytical Method for Robust Extraction of the Small-Signal Equivalent Circuit for SiGe HBTs Operating at Cryogenic Temperatures

We present a new analytical direct parameter-extraction methodology for obtaining the small-signal equivalent circuit of HBTs. It is applied to cryogenically operated SiGe HBTs as a means to allow circuit design of SiGe HBT low-noise amplifiers for cooled radio astronomy applications. We split the transistor into an intrinsic transistor (IT) piece modeled as a Pi-topology, and the quasi-intrinsic transistor (QIT), obtained from the IT after that the base resistance (R_b) has been removed. The relations between Z-Y-parameters of the IT and QIT are then established, allowing us to propose a new methodology for determining R_b. The present extraction method differs from previous studies in that each of the model elements are obtained from exact equations that do not require any approximations, numerical optimization, or post-processing. The validity of this new extraction methodology is demonstrated by applying it to third-generation SiGe HBTs operating at liquid-nitrogen temperature (77 K) across the frequency range of 2-22 GHz.