A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

Cell-plate line connecting complementary bit-line (C3)architecture for battery-operated DRAMs

In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line connecting complementary bit-line (C³) architecture, which realizes a large signal voltage on the bit-line pair and low soft error rate (SER) without degrading the reliability of the memory cell capacitor dielectric film, is proposed. This architecture requires no unique process technology and no additional chip area. With the test device using the 16-Mb DRAM process, a 130-mV signal voltage is observed at 1.5-V power supply with 1.6-μm×3.2-μm cell size. This architecture should open the path for the future battery-backup and/or battery-operated high-density DRAMs     

New three-dimensional memory array architecture for futureultrahigh-density DRAM

In this paper, a three-dimensional (3-D) memory array architecture is proposed. This new architecture is realized by stacking several cells in series vertically on each cell located in a two-dimensional array matrix. Therefore, this memory array architecture has a conventional horizontal row and column address and new vertical row address. The total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM when one bit-line has 1-Kbit cells and the same design rules are used. Moreover, an array area of 1-Mbit DRAM using the proposed architecture is reduced to 11.5% of normal DRAM using the same design rules. This proposed architecture's DRAM can realize small bit-line capacitance and small array area simultaneously. Therefore, this proposed 3-D memory array architecture is suitable for future ultrahigh-density DRAM     

A robust and low-power near-threshold SRAM in 10-nm FinFET technology

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation.     

A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A 1.6-GByte/s DRAM with flexible mapping redundancy technique andadditional refresh scheme

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

Design of a 128-mb SOI DRAM using the floating body cell (FBC)

A 128-Mb SOI DRAM has been developed featuring the floating body cell (FBC). To keep the cell data state from being degraded by the word-line (WL) disturb due to the charge pumping and to reduce the refresh busy rate, a sense amplifier (S/A) is arranged for every bit-line (BL) and replenishes data "1" cells' bodies with holes which are lost by the disturb in every read and write cycle. The power is reduced by operating the S/As asymmetrically between the selected and the unselected thanks to that the number of holes to be replenished in the unselected S/As for charge pumping is two order of magnitude smaller than that required for writing the data "1". The multi-pair averaging of dummy cells generates a very accurate reference current for distinguishing the data "1" and "0" and a Monte Carlo simulation shows that it achieves a sensing scheme robust enough to realize all good parts of the DRAM with a reasonable amount of redundancy. The cell's feature of quasi-nondestructive read-out is also advantageous for making an SRAM interface of the DRAM or hiding refresh from uses without sacrificing the access time.     

A transistorless-current-mode static RAM architecture

We propose a static memory architecture in which each bit consists of a single two-terminal device that is bistable in current. Current-mode operation of the memory array removes the need for cell-isolation transistors, thus, allowing huge increases in density over inverter-based SRAM and capacitor-based DRAM. Low power consumption and fast read/write speeds are ensured by taking advantage of the exponential nature of the memory's current-voltage characteristic     

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4×32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed     

基于FPGA技术的DRAM分时存取方法

介绍了一种基于现场可编程技术对DRAM进行读写和刷新操作的方法，根据现场可编程器件设计的特点，结合DRAM读写和刷新时序的要求，提出了同步化操作DRAM的思想，给出了具体同步化操作DRAM的实现方法，针对现场可编程器件设计中经常有多模块同时存取DRAM芯片的需求，提出了对DRAM芯片进行分时存取的方法，讨论了该方法的实现机制，结合具体的项目设计，给出了分时存取方法的关键时序，避开了复杂的DRAM控制器，节省了设计资源，简单方便地解决了DRAM操作的仲裁问题。     

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted2.1-V word line

This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V_ss) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-V_cc precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing ±20-ps quantization errors for clock recovery and skew elimination     

High density and low leakage current based SRAM cell using 45 nm technology

This article is based on the observation of a Complementary Metal-Oxide Semiconductor (CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. This 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 21.66% smaller than a conventional six-transistor SRAM cell using the same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The new 5T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45?nm technology.     

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.     

A 4-Mbit DRAM with 16-bit concurrent ECC

A 256 K-word×16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8-μm CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 μm² with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC     

A circuit design of intelligent cache DRAM with automaticwrite-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current     

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write,in addition to Write Assist and Read Isolation (WARI).Also a faster write back scheme is proposed for the half selected cells.A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write.The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read.Static noise margins for data read (RSNM),write (WSNM),read delay,write delay,data retention voltage (DRV),leakage and average powers have been calculated.The proposed cell was found to operate properly at a supply voltage as small as 0.41 V.A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay,pulse timing hardware requirements and power consumption.The proposed new WARI 8T cell shows better performance in terms of easier write,improved read noise margin,reduced leakage power,and less delay as compared to the existing schemes that have been available so far.It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.     

A compact low-power 4-port register file with grounded write bitlines and single-ended read operations

An area-efficient 4-port register file with low power consumption is presented for mobile application processors. Area efficiency at array level is achieved with a novel compact bitcell that supports single-ended one-sided read operations using the direct read access mechanism and single-ended write operations. A write-assist technique ensures robust operation down to 0.75 V. Single-ended one-sided read operations help maintain sufficient bitcell stability at 0.75 V. Factors that contribute toward low power consumption include grounded write bitlines, bitcells with low leakage currents, individual read clock generators for top and bottom halves of the array, and smaller wordline buffers and capacitance due to a smaller bitcell. For a 2-Kib array implemented in TSMC 65 nm low power (LP) dual-V_t CMOS process, the proposed design achieves 17.8% reduction in silicon area, 19.6% lower active power, and 12.8% lower standby power when compared to the conventional 4-port dual-V_t register file. These benefits are obtained by trading off operating frequency at voltages below the nominal, read and write bitcell noise margins, and data retention voltage.