Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.     

The role of the insulator in determining 1/f noise in Hg1-xCdxTe integrating MIS devices

The low frequency 1/f noise charge found in Hg_1-xCd_xTe integrating metal-insulator-semiconductor (MIS) devices operating at 40K and low bias above threshold is found to be independent of integration time. The signal theory of random processes is utilized to demonstrate that 1/f noise charge resulting from carrier number fluctuations due to insulator traps should not depend on integration time, while 1/f noise charge resulting from 1/f noise in any current filling the MIS well should be proportional to integration time. This distinction allows for the determination of effective insulator trap densities from low temperature 1/f noise data on simple MIS structures. The technique is applied to a number of n-channel and p-channel devices and the effective trap densities in ZnS are determined.     

Modeling of noise for p-channel DG-FinFETs

The noise performance of p-channel Double Gate FinFETs has been studied with varying structural parameters. The effects of mobility degradation due to velocity saturation, carrier heating and channel length modulation have been taken into consideration for an accurate modeling of noise. The dependence of mobility fluctuations on the inversion carrier density has been incorporated. This has been validated by the experimental results. The noise behavior of p-channel device has been compared to that of a corresponding n-channel device. It has been observed that noise in p-channel device is comparatively higher due to higher number of oxide-trap density in it. Further, it has been noted that with the same trap density in both p-channel and n-channel device, the flicker noise in the p-channel device is lower than that of the corresponding n-channel device.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Subthreshold current of dual-gate MOSFET's

The subthreshold conduction in dual-gate MOS transistors is investigated. The subthreshold current is calculated both in the long-channel case and the short-channel case by means of simple models. Good agreement is found between theory and experimental results obtained through measurements on overlapping-gate n-channel devices. As an application of the subthreshold current analysis, the low-frequency transfer inefficiency in bucket-brigade devices (BBD's) is evaluated. The theoretical result agrees well with measurements carried out on p-channel nonoverlapping-gate devices.     

On the intrinsic limits of pentacene field-effect transistors

Performance limits for pentacene based field-effect transistors are investigated using single- and polycrystalline devices. Whereas the charge transport in single crystalline devices is band-like with mobilities up to 10⁵ cm²/V s at low temperatures, temperature-independent or thermally activated charge transport can be observed in polycrystalline thin film transistors depending on the growth conditions. Trapping and grain boundary effects significantly influence the temperature dependence of the field-effect mobility. Furthermore, the device performance of p-channel transistors (mobility, on/off ratio, sub-threshold swing) decreases slightly with increasing trap densities. However, the formation of an electron accumulation layer (n-channel) is significantly stronger affected by trapping processes in the thin film devices. Single crystalline p-channel devices exhibit at room temperature mobilities as high as 3.2 cm²/V s, on/off-ratios exceeding 10⁹, and sub-threshold swings as low as 60 mV/decade. Slightly diminished values are obtained for transistors working as n-channel devices (2 cm²/V s, 10⁸, and 150 mV/decade).     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Performance of CMOS devices in silicon-on-sapphire films after solid-phase epitaxial growth with rapid electron-beam heating

The crystal quality of 0.3-µm-thick as-grown epitaxial silicon-on-sapphire (SOS) was improved using solid-phase epitaxy (SPE) by implantation with silicon to 10¹⁵ions/cm²at 175 keV and rapid annealing using electron-beam heating, n-channel and p-channel transistor mobilities increased by 31 and 19 percent, respectively, and a reduction in ring-oscillator stage delay confirmed that crystal defects near the upper silicon surface had been removed. Leakage in n-channel transistors was not significantly affected by the regrowth process but for p-channel transistors back-channel leakage was considerably greater than for the control devices. This is attributed to aluminum released by damage to the sapphire during silicon implantation.     

Spectroscopic charge pumping: A new procedure for measuringinterface trap distributions on MOS transistors

An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

Fabrication of Si MOSFET's using neutron-irradiated Silicon as semi-insulating substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The mobility of carrier in the channel is about 100 cm²/V . s for p-channel MOSFET's and 300 cm²/V . s for n-channel devices. This structure has inherent advantages such as crystallographically single crystalline.     

Low-frequency noise in near-fully-depleted TFSOI MOSFETs

Low-frequency (1/f) noise in near-fully-depleted Thin-Film Silicon-On-Insulator (TFSOI) CMOS transistors designed for sub-l-V applications is investigated in the subthreshold region, linear region, and saturation region of operation for the first time. The noise in these surface-channel devices is composed of a bias invariant 1/f component and a bias dependent generation-recombination (G/R) component that becomes enhanced in the subthreshold region of operation for both n- and p-channel MOSFETs. Results presented in this letter are consistent with the noise being dominated by a number fluctuation model. These results demonstrate that the bias independent 1/f noise spectrum of the n-channel TFSOI MOSFET is comparable to the 1/f noise level found in conventional bulk silicon submicron CMOS fabrication processes     

Fabrication of Si MOSFET's Using Neutron-Irradiated Silicon as Semi-Insulating Substrate

The feasibility of a novel silicon-on-semi-insulating substrate structure has been demonstrated. MOS field-effect transistors (MOSFET's) are fabricated on neutron-irradiated silicon wafers which are used as semi-insulating substrates. In order to keep the substrate semi-insulating, laser annealing is used to make the semiconducting layer, and to activate the impurities implanted in the semiconducting layer, and plasma anodization is employed to grow the gate oxide. The, mobility of carrier in the channel is about 100 cm/sup 2//V /spl dot/s for p-channel MOSFET's and 300 cm/sup 2//V /spl dot/s for n-channel devices. This structure has inherent advantages such as crystallographicafly single crystalline.     

Flicker noise in CMOS transistors from subthreshold to stronginversion at various temperatures

Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation     

A JFET-CMOS radiation-tolerant charge-sensitive preamplifier

A monolithic charge-sensitive preamplifier based on n-channel junction field-effect transistors (JFETs) and p-channel MOS has been realized for applications with microelectrode detectors in elementary particle physics. Radiation resistance tests carried out with the preamplifier exposed to γ-rays emitted by a ⁶⁰Co source have shown no significant increase of the equivalent noise source up to 150-krd absorbed dose     

Comparison between the effects of positive noncatastrophic HBM ESDstress in n-channel and p-channel power MOSFETs

The effect of noncatastrophic positive human body model (HBM) electrostatic discharge (ESD) stress on n-channel power MOSFETs is radically different from that on p-channel MOSFETs. In n-channel transistors, the stress causes negative shifts of the current-voltage characteristics indicative of positive charge trapping in the gate oxide. In p-channel transistors, the stress increases the drain-to-source leakage current, probably due to localized avalanche electron injection from the p-doped drain     

Effects of operating temperature on electrical parameters in ananalog process

The variation of basic MOS device properties with operating temperature is examined. These devices include both n-channel and p-channel transistors, resistors, junction diodes, and precision capacitors. The theory of such variations is briefly examined, and fits to empirical expressions are graphically derived. Implications of such variations are briefly explored     

MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.