High-speed low-power voltage-programmed driving scheme for AMOLED displays

A new voltage-programmed driving scheme named the mixed parallel addressing scheme is presented for AMOLED displays, in which one compensation interval can be divided into the first compensation frame and the consequent N-1 post-compensation frames without periods of initialization and threshold voltage detection. The proposed driving scheme has the advantages of both high speed and low driving power due to the mixture of the pipeline technology and the threshold voltage one-time detection technology. Corresponding to the proposed driving scheme, we also propose a new voltage-programmed compensation pixel circuit, which consists of five TFTs and two capacitors(5T2C). In-Zn-O thin-film transistors(IZO TFTs) are used to build the proposed 5T2C pixel circuit. It is shown that the non-uniformity of the proposed pixel circuit is considerably reduced compared with that of the conventional 2T1C pixel circuit. The number of frames(N) preserved in the proposed driving scheme are measured and can be up to 35 with the variation of the OLED current remaining in an acceptable range. Moreover, the proposed voltage-programmed driving scheme can be more valuable for an AMOLED display with high resolution, and may also be applied to other compensation pixel circuits.     

A self-consistent analytic threshold voltage model for thin SOI n-channel MOSFETs

An accurate analytical threshold voltage model is presented for fully-depleted SOI n-channel MOSFETs having a metal-insulator-semiconductor-insulator-metal structure. The threshold voltage is defined as the gate voltage at which the second derivative of the inversion charge with respect to the gate voltage is maximum. Since the inversion charge is proportional to the drain current at low bias, the model is self-consistent with the measurement scheme when the threshold voltage is measured as the gate voltage at which the variation of the transconductance at low drain bias is maximum. Numerical simulations show good agreement with the model with less than 3% error.     

Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.     

Forward gated-diode measurement of filled traps in high-fieldstressed thin oxides

The forward gated-diode monitoring technique can find its potential applications in assessing the filled traps in MOSFET thin oxides, which are subjected to high-field stressing and then followed by a hot-electrons filling scheme. Our measurement of the gate voltage shift associated with the forward current peak produces a power law relation between the filled trap density and the electron stress fluence, indeed in close agreement with that obtained by MOSFET threshold voltage shift     

GIS金属法兰孔处的VFTO测量系统设计

内置式VFTO的测量传感器体积大、安装困难,不适用于在运的特高压GIS。针对以上缺陷,文中设计了一种适用于GIS金属法兰孔处的VFTO测量系统。该系统采用FPC电容分压与二次阻容分压器结合的方案,实现了GIS外置小型化的VFTO测量。根据金属法兰孔的尺寸及测量系统的性能要求,对FPC进行结构、尺寸设计,研制了电容分压探头。为改善测量系统的性能,设计了宽频阻容分压器,并通过实测的方式对匹配电阻与同轴电缆的参数进行优化。试验结果表明,VFTO测量系统的带宽为22.45 Hz~111.45 MHz,分压比为112 790,可以准确溯源波形,满足VFTO测量要求。     

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated     

VTH-hopping scheme to reduce subthreshold leakage forlow-power processors

In order to suppress the power consumption in low-voltage processors, a threshold voltage hopping (V_TH-hopping) scheme is proposed where the threshold voltage is dynamically controlled through software depending on a workload. V_TH-hopping is shown to reduce the power to 18 % of the fixed low-threshold voltage circuits in 0.5-V supply voltage regime for multimedia applications. A positive back-gate bias scheme with V_TH-hopping is presented for the high-performance and low-voltage processors. In order to verify the effectiveness of V_TH-hopping, a small-scale RISC processor with V_TH-hopping capability and the positive back-gate bias scheme is fabricated in a 0.6-μm CMOS technology. MPEG4 encoding is simulated based on the measured data. The result shows that 86% power saving can be achieved by using V_TH-hopping compared with the fixed positive back-gate bias scheme     

On the temperature variation of threshold voltage of GaAs MESFETs

The authors have investigated the temperature dependence of the threshold voltage of depletion-mode GaAs MESFETs with epitaxially grown n channels. An approach to threshold shift analysis that allows direct comparison with threshold measurement is taken. The contributions from various temperature-dependent effects to the threshold-voltage shift were studied, including the built-in voltage of the Schottky barrier, deep-level transients, capping layer effects, the substrate-channel built-in voltage, and the k factor which is related to channel mobility. A quasi-DC method for threshold voltage measurement, which enables threshold voltage to be measured as a function of temperature with minimum deep-level transient effect is reported. A method has also been developed to measure the temperature dependence of built-in voltage which is completely free from transient effects. The results show that the major contributors to the temperature variation of threshold voltage are the temperature dependence of the Schottky barrier built-in voltage and the effect of the capping layer     

Class AB output stage for low voltage CMOS op-amps with accuratequiescent current control

A new class AB output stage for CMOS op-amps, with accurate quiescent and minimum current control, is proposed. The proposed stage can be operated with a supply voltage close to the threshold voltage of the transistor. A dynamic biasing scheme allows it to operate over a wide range of supply voltages. Simulation results are provided that are in good agreement with expected values     

Three-dimensional analytical subthreshold models for bulk MOSFETs

Three-dimensional device-physics-based analytical models are developed for subthreshold conduction in uniformly doped small geometry (i.e., simultaneously short channel and narrow width) bulk MOSFETs, for various isolation schemes. Inverse-narrow width effects, where the threshold voltage decreases with decreasing channel width, are predicted by the model for trench isolated MOSFETs. For LOGOS isolated MOSFETs, conventional narrow width effects, where the threshold voltage increases due to decreasing channel width, are predicted. The narrow width effects are found to be comparable to the short channel effects in the absence of significant applied drain biases. However, for larger drain biases, the short channel effects outweigh the narrow width effects due to the weaker potential perturbation at the device width edges compared to the drain end. Unlike the threshold voltage, the subthreshold swing of the device is found to increase with reduced device dimensions regardless of the isolation scheme since both conventional and inverse narrow width effects result in weaker control of the surface potential by the gate     

Improvements to "A new AC measurement technique to accurately determine MOSFET constants"

Modifications and improvements to the measurement technique described in [1] are presented. In particular, the iterative procedure used to obtain an accurate value for device threshold voltage has been eliminated and replaced by direct calculation. The measurement technique has also been applied to a modulation of the substrate potential in order to obtain an estimate of threshold parameters.     

Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell

A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.     

A new threshold-voltage model for small-geometry buried-channel MOSFETs

This paper presents an analytic model for the threshold voltage of small-geometry buried-channel MOSFETs, in which the implanted buried-channel profile is approximated by a step profile. Based on the energy-band diagram, the threshold voltage of a buried-channel MOSFET is derived, in which the flatband voltage is physically defined. Using a new charge-sharing scheme, the threshold-voltage model considering the short-channel effect is calculated analytically. Similarly, based on the charge-sharing scheme, the narrow-width effect considering the field implant encroachment under the bird's beak is calculated. Combining both short-channel and narrow-width effects, the threshold-voltage model for small-geometry buried-channel MOSFETs is developed. In order to test the validity of the model, the buried-channel MOSFETs were fabricated in a production line and the threshold voltages were measured. Comparisons between the measured threshold voltage and the present model have been made. It is shown that satisfactory agreement has been obtained for wide ranges of channel lengths, channel widths and applied back-gate biases.     

A new SOI inverter using dynamic threshold for low-powerapplications

A new SOI inverter using the dynamic threshold (DT) that lowers threshold voltage of MOSFET only in active operation of a logic circuit is proposed for high-speed and low-power applications. The dynamic threshold scheme is realized by dynamically biasing the body of MOSFET's. The SOI MOSFET's have been designed and fabricated to take full advantage of the reverse body effect which is affected by many device parameters. From the measurements and simulations, the proposed scheme is shown to be useful in the buffer with large load conditions and low supply voltage if the SOI MOSFET's are properly designed     

A new and flexible scheme for hot-electron programming ofnonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices     

背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响

LOCOS隔离的SOI器件的性能强烈依赖于其背栅特性,而背栅应力会影响到背栅的特性。常温下在SOI器件的背栅上施加大电压并持续30秒以上可以显著改变背栅的阈值电压。这种改变是稳定的和时不变的。对NMOS加正的背栅压和对PMOS加负的背栅压都可以提高其背栅阈值电压。实验结果表明沿着硅岛的边缘有一条从源到漏的寄生漏电通道,而且将栅,源,漏接地并在背栅上加大的偏压可以强烈影响漏电通道。因此我们可以得到结论,背栅应力会影响与漏电流直接相关的背栅阈值电压。     

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique

This brief describes an ultralow-voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultralow voltage. The chip is fabricated in a 0.13- $muhbox{m}$ standard CMOS process with a 0.5-V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610 MHz with a 0.5-V power supply voltage. At 550 MHz, the measured root-mean-square jitter and peak-to-peak jitter are 8.01 and 56.36 ps, respectively. The total power consumption of the PLL is 1.25 mW, and the active die area of the PLL is 0.04 $hbox{mm}^{2}$.      

一种极低门限的电压比较器设计

针对单电源供电集成电路中高精度低门限电压比较器设计的难点,设计了一种具有极低门限的新型电压比较器,该比较器电路利用三极管发射结压差与热电压成正比例关系来设置比较器低门限阈值点,满足了许多需要用到此类比较器而用传统方法无法满足要求的场合.电路结合一款基于准谐振操作的开关电源控制芯片,在0.6 μm BCD工艺下实现,利用Workview、Hspice等软件对电路进行仿真、验证,比较器门限电压和迟滞宽度可低至毫伏级,且可以根据需要方便地进行调节,并有很好的精度和动态响应特性,具有结构简单和通用性好的特点,可广泛应用于不同的SoC环境.     

Preprocessor modeling of parameter and geometry dependences of short and narrow MOSFET's for VLSI circuit simulation, optimization, and statistics with SPICE

A parameter measurement and modeling method is described for the SPICE-2 level-3 MOSFET. Geometry dependences are modeled outside the simulator with simple polynomials which are incorporated into a preprocessor for parameter generation and circuit file construction. Operating point dependences of threshold voltage, body effect, and channel width are incorporated into an enhanced device model inside the simulator. The method is of general application and can be applied to any circuit simulator containing any transistor model. Use of the preprocessor enables the transistor model in the simulator to be reduced to its simplest and computationally shortest form, eliminates the task of parameter listing for the circuit designer, and provides a means for automated circuit design, optimization, reliability studies, and yield statistics.     

Design of Diode Type Un-Cooled Infrared Focal Plane Array Readout Circuit

The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array.