Positive temperature coefficient of breakdown voltage in 4H-SiC pnjunction rectifiers

It has been suggested that once silicon carbide (SiC) technology overcomes some crystal growth obstacles, superior SiC semiconductor devices would supplant silicon in many high-power applications. However, the property of positive temperature coefficient of breakdown voltage, a behavior crucial to realizing excellent power device reliability, has not been observed in 4H-SiC, which is presently the best-suited SiC polytype for power device implementation. This paper reports the first experimental measurements of stable positive temperature coefficient behavior observed in 4H-SiC pn junction rectifiers. This research indicates that robust 4H-SiC power devices with high breakdown reliability should be achievable after SiC foundries reduce material defects such as micropipes, dislocations, and deep level impurities     

Simple precision bias circuit for medium-power amplifiers

Describes a new bias current regulation circuit for single-stage bipolar and FET amplifiers which achieves high precision and simplicity through a combination of feedback error amplifier with bandgap reference. The internally generated reference voltage can be preset between 100-200 mV. The approach is ideal for applications where the overhead voltage must be minimized to reduce power dissipation, and typically offers <0.5% regulation and ⩽40 ppm/°C temperature coefficient. The authors present three common applications which demonstrate the unique advantages of the new topology     

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization

This paper presents a multiplier power reduction technique for low-power DSP applications through utilization of coefficient optimization. The optimization is implementation dependent in that the multipliers are assumed to be designed in either ASIC or full-custom architectures for general purpose multiplication. The paper first describes a model characterizing the power consumption of the multiplier. Then the coefficient optimized made based on this model. This methodology is applicable to multiplications requiring a large set of coefficients and random data sets. We can accurately estimate the actual power dissipation of the multipliers using the characterization technique. The coefficient optimization based on the power model can save as much as 34.02%.     

A programmable pipelined digital differential matched filter forDSSS receiver

A programmable pipelined digital differential matched filter (PDMF) implemented for a direct sequence spread spectrum receiver is proposed in this paper. To reduce the power consumption, the PDMF architecture is based on the synchronization combined PN code phase acquisition algorithm. Compared with the conventional PN code phase acquisition algorithm, the theoretical analysis result indicates that the PDMF acquires both power efficient and preferable detection. Depending on different applications, programmability allows the PDMF to implement 3-tap, 5-tap, or 11-tap Barker codes with the same hardware but different precisions for each tap coefficient. For short tap Baker codes, the architecture could adopt more precision on each tap coefficient to resist the channel noise. Simulation results also show that there are fewer errors of high sample precision with the same tape     

基于梯形积分PI控制的LED反激式开关电源的研究

LED照明具有节能、安全、环保的特性,作为一个新兴的技术领域,在最近几年得到很大发展。LED是典型的电流驱动器件,精确控制驱动电流,可决定光效、电源效率、散热等许多参数。为了降低电流纹波系数,在高频反激式开关电源中,采用梯形积分PI控制方法。通过搭建基于MATLAB/Simulink的反激式开关电源模型,对梯形积分PI控制方法进行了仿真。仿真结果表明,梯形积分PI控制方法能有效的减小电源的纹波电流,电流纹波系数降低到1.5%,达到了控制目的。     

基亏梯形积分PI控制的LED反激式开关电源的研究

LED照明具有节能、安全、环保的特性,作为一个新兴的技术领域,在最近几年得到很大发展。LED是典型的电流驱动器件,精确控制驱动电流,可决定光效、电源效率、散热等许多参数。为了降低电流纹波系数,在高频反激式开关电源中,采用梯形积分PI控制方法。通过搭建基于MATLAB／Simulink的反激式开关电源模型,对梯形积分PI控制方法进行了仿真。仿真结果表明,梯形积分PI控制方法能有效的减小电源的纹波电流,电流纹波系数降低到1．5％,达到了控制目的。     

第二代功率因素校正解决方案

在所有的电力电子设备中获得最高的转换效率永远是人们追求的头等目标。在一些新标准的规定下目前很多功率转换设备都必须具备有效功率因素校正功能。对电子元件而言额外的功率损耗会增加散热器和整个设备的体积。本文研究的目的就是在不断增加设备成本的情况下将损耗降到最低。     

A Low Power Folded Mixer for UWB System Applications in 0.18-μm CMOS Technology

This letter presents a wideband mixer using a commercial 0.18-mum CMOS technology process for ultra-wideband (UWB) system applications. To achieve wideband frequency response and low dc power consumption for UWB system applications, the folded approach is utilized to reduce supply voltage as well as dc power consumption, and wideband input matching network is used to achieve wideband frequency response. The measured results show that the proposed mixer demonstrates a wideband frequency response from 0.2 to 16GHz with a conversion gain of better than 5.3dB. The dc power consumption is 15mW under a supply voltage of 1.8V, with a compact size of 0.68mmtimes0.65mm     

新型结构IGBT功率模块——flowPHASE 0

现在绝大多数变频器电路的设计，都是基于印制电路板（PCB）进行的。对于小功率变频器，这样的设计可以使得变频器结构更加紧凑，实现小型化设计；对于中大功率变频器，由于现有功率模块的结构特点，通用的方法是通过铜排走线，存在的问题是成本高，寄生电感大，EMI问题严重。泰科电子（Tyco）针对这些问题，推出了基于完全PCB布线的600V，1200V IGBT功率模块，功率范围覆盖了15kW到30kW。     

A flexible active and reactive power control strategy for avariable speed constant frequency generating system

Variable-speed constant-frequency generating systems are used in wind power, hydroelectric power, aerospace, and naval power generation applications to enhance efficiency and reduce friction. In these applications, an attractive candidate is the slip power recovery system comprising a doubly excited induction machine or doubly excited brushless reluctance machine and PWM power converters with a DC link. In this paper, a flexible active and reactive power control strategy is developed, such that the optimal torque-speed profile of the turbine can be followed and overall reactive power can be controlled, while the machine copper losses have been minimized. At the same time, harmonics injected into the power network have also been minimized. In this manner, the system can function as both a highly-efficient power generator and a flexible reactive power compensator     

一种低功耗2D DCT/IDCT处理器设计

设计了一种低功耗的2D DCT/IDCT处理器。为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。常系数乘法器是该处理器的一个重要部件,文中基于并行乘法器结构设计了一种新型的低功耗常系数乘法器,它采用了CSD编码、Wallace Tree乘法算法,结合采用了截断处理、变数校正的优化技术,使得2D DCT/IDCT处理器整体性能有较大提高。设计的时钟频率为100 MHz,可以满足MPEG2 MP@HL实时解码的应用。采用SMIC0.18μm工艺进行综合,该2D DCT/IDCT处理器的面积为341 212μm2,功耗为14.971 mW。通过与其他结构的2DDCT/IDCT处理器设计分析与比较,在满足MPEG2 MP@HL实时解码应用的同时,实现了较低的功耗。     

PSAR: power-source-aware routing in ZigBee networks

ZigBee is a recent wireless networking technology built on IEEE 802.15.4 standard and designed especially for low-data rate and low-duty cycle applications such as home and building automation and sensor networks. One of the primary goals of ZigBee is low power consumption and therefore long-living networks. Despite this goal, current network formation and routing protocols described in the ZigBee specification do not fully address power consumption issues. In this work, we propose a distributed routing algorithm to reduce power consumption of battery-powered devices by routing the communication through mains-powered devices whenever possible and consequently increasing the overall network lifetime. The proposed algorithm works on tree topologies supported by ZigBee and requires only minor modifications to the current specification. Our ns-2 simulation results showed that the algorithm is able to reduce the power consumption of battery-powered devices significantly with minimal communication overhead.     

采用Soft-Skip无噪声待机模式的反激电源

本文介绍了采用Soft-Skip开关模式以降低电源待机功耗的原理。这种待机状态下的开关模式可以有效降低因开关频率过低产生的音频噪声,并且可以对进入Soft-Skip模式的电平进行调整以适应不同的负载需求。最后,试制了一台输出为12V／5A的反激电源对这种待机模式进行验证。     

基于电源管理技术降低嵌入式系统功耗的研究

嵌入式处理器产品既要求提高其性能又要求降低功耗,这是互相矛盾的两个方面。但是,高性能处理必须增加计算复杂度并加快时钟速率,如果采用权宜之计的节省功耗设计方案,是很难实现的。介绍利用B lackfin数字信号处理器系列产品固有的动态电源管理方法来管理功耗,以便在具体的嵌入式应用中优化性能与功耗的关系,较好地解决降低嵌入式系统功耗问题。     

Instruction buffering to reduce power in processors for signalprocessing

Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8×8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%     

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding

In embedded control applications, system cost and power/energy consumption are key considerations. In such applications, program memory forms a significant part of the chip area. Hence reducing code size reduces the system cost significantly. A significant part of the total power is consumed in fetching instructions from the program memory. Hence reducing instruction fetch power has been a key target for reducing power consumption. To reduce the cost and power consumption, embedded systems in these applications use application specific processors that are fine tuned to provide better solutions in terms of code density, and power consumption. Further fine tuning to suit each particular application in the targeted class can be achieved through reconfigurable architectures. In this paper, we propose a reconfiguration mechanism, called Instruction Re-map Table, to re-map the instructions to shorter length code words. Using this mechanism, frequently used set of instructions can be compressed. This reduces code size and hence the cost. Secondly, we use the same mechanism to target power reduction by encoding frequently used instruction sequences to Gray codes. Such encodings, along with instruction compression, reduce the instruction fetch power. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs as benchmarks. Our scheme reduces the code size by over 10% and the energy consumed by over 40%. *A preliminary version of this paper has appeared in the International Conference on Computer Aided Design (ICCAD-2001), San Jose, CA, November 2001.     

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuit-level techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X.     

可用于音频功放的过温保护电路设计

在分析温度对集成电路芯片工作可靠性、安全性影响的基础上,利用与温度成正比的PTAT电流和负温度系数的PN结电压,设计了一种低功耗的过温保护电路.该电路结构简单、工艺兼容性好、具有良好的移植性,可以应用于音频功放及各类集成电路芯片中.同时该电路还具有温度的迟滞特性,可以更好地保护芯片,避免振荡的产生.0.35 μm Cadence Specture仿真结果表明,该电路功耗低且可以实现高精度的过温保护功能.     

Genetic algorithm optimization of a hybrid analog/digital predistorter for RF power amplifiers

This study presents a genetic algorithm optimization of a hybrid analog/digital predistorter, in order to reduce the intermodulation distortion (IMD) caused by the nonlinear properties of the radio frequency (RF) power amplifier (PA). Designed predistorter based on polynomial work function and the coefficient of the polynomial is optimized in order to reduce IMD by spectrum monitoring. The design procedure and validation of predistorter have been carried out by Agilent-ADS2005A. In order to validate the predistorter two different modulation schemes as CDMA and 16-QAM have been used. Also in order to verifying the linearization a test power amplifier circuit has been examined including Motorola MOSFET MRF9742 showing the nonlinear characteristics with memory. Simulations have been shown that adjacent channel power ratio (ACPR) improvements were acceptable for both CDMA and 16-QAM modulation schemes.     

高功率双包层光纤激光器温度分布的有限元分析

高功率双包层光纤激光器的热效应严重制约光纤激光器的输出功率和光束质量。首先通过求解热传导方程得到简化情况下的温度解析解;然后，利用有限元方法对不同情况下的温度分布进行模拟计算。通过模拟计算得到：外包层聚合物材料的热传导系数对光纤的温度分布影响较小，因而在近似计算时可以认为纤芯及内、外包层热传导系数相等;外包层表面的对流换热系数对温度分布影响较大，增大对流换热系数，可以有效地降低光纤激光器的热效应;外包层光纤半径的大小对光纤激光器的温度分布也有影响。所得的结果为设计实现千瓦级光纤激光器提供了参考。