多点数高精度低存储的FFT处理器设计

提出了一种新的基于基23算法单路径反馈流水线结构的FFT处理器.通过对数据通路的动态调整,解除了变换点数必须是8的幂次的限制,可高效实现任意2n点的FFT/IFFT变换.并将自定义浮点格式引入流水线,同时在流水线输入端添加预处理单元,在不引入过多逻辑的情况下,有效的提高了FFT的变换精度,同时存储器的使用量降低10%.     

An architecture for a VLSI FFT processor

We propose a new VLSI architecture for an FFT processor. Our architecture uses few processing elements and can be laid out in a mesh-interconnected pattern. We show how to compute the discrete Fourier transform at n points with an optimal speed-up as long as the memory is large enough. The control is shown to be simple and easily implementable in VLSI.     

A VLSI array processor for 16-point FFT

An implementation of a two-dimensional array processor for fast Fourier transform (FFT) using a 2-μm CMOS technology is presented. The array processor, which is dedicated to 16-point FFT, implements a 4×4 mesh array of 16 processing elements (PEs) working in parallel. Design considerations in both the chip level and the PE level are examined. A layout design methodology based on bit-slice units (BSUs) results in a very simple design, easy debugging, and a regular interconnection scheme through abutment. It contains about 48,000 transistors on an area of 53.52 mm², excluding the 83-pad area, and operation is on a 15-MHz clock. The array processor performs 24.6 million complex multiplications per second, and computes a 16-point FFT in 3 μs     

A dynamic scaling FFT processor for DVB-T applications

This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-/spl mu/m single-poly six-metal CMOS process with core area of 4.84 mm/sup 2/. Power dissipation is about 25.2 mW at 20 MHz.     

Advanced constant multiplier for multipath pipelined FFT processor

A novel method for reducing the number of equivalent complex multipliers for a multipath mixed-radix 128-point FFT processor using an advanced constant multiplier is proposed.     

DMB-T系统中FFT模块的设计与实现

介绍了地面数字多媒体/电视广播传播系统(DMB-T)中3 780点FFT模块的重要作用.考虑到不适合直接利用现已成熟的基-2和基-4的算法,提出一种全并行流水结构的3 780点FFT的设计和实现方案.该方案采用WFTA算法和PFA算法,把3780分解为7×9×5×4×3共5级的流水线结构.通过对整个系统的仿真与硬件实现,证明该方案性能上能够满足TDS-OFDM系统的信噪比要求.     

3780点FFT处理器的研究

3780点FFT模块是地面数字多媒体／电视广播传播系统（DMB—T）中的重要模块之一，由于该模块不能直接利用现已成熟的基-2和基-4的算法，故给出了三种实现3780点FFT的算法和处理器结构，分别是内插成4096点的FFT算法、混合基FFT算法和综合分解算法，并对各种方法的优缺点进行了讨论。     

基于CORDIC的FFT处理器设计

波束形成是阵列信号处理过程的一个重要步骤,它在雷达、地质勘探、医学成像领域起着关键的作用并得到了广泛的应用。在声呐系统中,FFT处理器是波束形成器的关键部件,论文中引用了CORDIC算法,并对比了基2、基4等时域FFT算法的区别,根据基本原理和流程最终选定了基4算法,将其有效地和CORDIC算法结合起来。设计了一款基于CORDIC算法的FFT处理器。采用流水线方式,形成了5级蝶形算法,满足了FFT运算要求。     

基于FPGA的FFT处理器设计

针对快速傅里叶变换（FFT）算法的结构和特点,提出了一种基于现场可编程门阵列（FPGA）设计FFT运算的方案。该方案采用基2算法以及单元结构的设计思路,对FFT处理器合理模块化,用VHDL语言对各个模块编程,并在Quartusll软件环境下综合仿真,时序分析结果与Matlab计算结果相一致验证了设计的正确性。FFT与FPGA相结合提高了运算速度,扩大了FFT的应用领域。     

Efficient microcoded processor design for fixed rate DFT and FFT

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware-sharing is required as in microcoded architectures. In this paper, very efficient application-specific realizations spanning a wide throughput range are proposed for both DFT and FFT algorithms. Novel single-cycle address computations are presented for the FFT to obtain these results. Trade-offs between the architectural alternatives are provided too. These designs have been used as test-vehicles for the architectural strategy in an automated synthesis tool-box tuned towards signal processing applications.This research has been sponsored in part within the context of the ESPRIT97 project by the EC and the industrial partners Philips, Siemens, BTMC/Alcatel and Silvar/Lisco.     

可变长数据全并行FFT地址生成方法

本文通过对混合基4/2 FFT算法的分析,在优化采样数据、旋转因子存储及读取方法的基础上,提出了将N=2m点,m为奇、偶两种情况的地址产生统一于同一函数的算法,并设计了简单的插入值产生及快速插入位置控制电路,从而用一个计数器、同一套地址产生硬件,通过简单的开关模式控制,可实现任意长度FFT变换的地址产生单元,该地址产生单元在一个时钟周期内产生读取所需旋转因子及并行访存4个操作数的地址.本文设计的FFT处理器每周期完成一个基4或2个基2蝶式运算,在吞吐率高、资源少的基础上实现了处理长度可编程的灵活性,同时避免了旋转因子重复读取,降低功耗.     

Scheduling techniques for reducing processor energy use in MacOS

The CPU is one of the major power consumers in a portable computer, and considerable power can be saved by turning off the CPU when it is not doing useful work. In Apple's MacOS, however, idle time is often converted to busy waiting, and generally it is very hard to tell when no useful computation is occurring. In this paper, we suggest several heuristic techniques for identifying this condition, and for temporarily putting the CPU in a low‐power state. These techniques include turning off the processor when all processes are blocked, turning off the processor when processes appear to be busy waiting, and extending real time process sleep periods. We use trace‐driven simulation, using processor run interval traces, to evaluate the potential energy savings and performance impact. We find that these techniques save considerable amounts of processor energy (as much as 66%), while having very little performance impact (less than 2% increase in run time). Implementing the proposed strategies should increase battery lifetime by approximately 20% relative to Apple's current CPU power management strategy, since the CPU and associated logic are responsible for about 32% of power use; similar techniques should be applicable to operating systems with similar behavior. This revised version was published online in June 2006 with corrections to the Cover Date.     

A novel parallel prefix adder for optimized Radix-2 FFT processor

Multidimensional Systems and Signal Processing - The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource...     

OFDM系统中高速FFT处理器的FPGA实现

针对OFDM系统中FFT处理器的设计要求,选择并具体分析FFT基4-DIF算法流程,并利用现场可编程设计开发了高速FFT信号处理器。本设计采用Verilog HDL语言进行描述,并通过了仿真和验证。     

Improved implementation of FFT algorithm on a high-performance processor

The letter demonstrates an FFT algorithm implemented on the 68000 microprocessor that can calculate a 256-point transform in less than 48 ms. The algorithm employs an interesting method of scaling data to overcome overflow.     

用于MB-OFDM UWB系统的FFT/IFFT处理器的设计与实现

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。该处理器采用基24算法进行FFT运算,利用8路并入并出的流水线结构实现该算法,提高了处理器的数据吞吐率,降低了芯片功耗。提出了一种新颖的数据处理方式,在保证信噪比的情况下节约了逻辑资源。在乘法器的设计环节,针对UWB系统的具体特点,在结构上对乘法器进行了改进和优化,提高了乘法器的性能。最后,设计的FFT/IFFT处理器采用TSMC 0.18μm CMOS标准工艺库综合,芯片的内核面积为0.762mm2(不含测试电路)。在1.8V,25℃条件下,最大工作时钟317.199MHz,在UWB典型的工作频率下,内核功耗为33.5304mW。     

DVB-T中的FFT设计与实现

文章首先对DVB-T系统的概念和应用进行了阐述,接着重点对其中的FFT模块进行研究.由于DVB-T系统存在2K/8K模式,为方便起见,我们选择采用2K模式进行FFT模块的设计与实现,包括算法实现、系统架构设计、FPGA实现、仿真.最后对仿真结果进行了分析.     

A 1-GS/s FFT/IFFT processor for UWB applications

In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s.