共查询到20条相似文献,搜索用时 156 毫秒
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提出了一种二维离散小波变换的FPGA实现方法,并对设计结果进行了功能和时序仿真。本设计方案不仅可以满足实时性的要求,而且采用模块化设计,可以实现多级小波变换。 相似文献
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二维离散小波变换的FPGA实现 总被引:1,自引:0,他引:1
提出了一种二维离散小波变换的FPGA实现方法.并对设计结果进行了功能和时序仿真。本设计方案不仅可以满足实时性的要求,而且采用模块化设计,可以实现多级小波变换。 相似文献
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用开关电流技术实现小波变换的关键是实现小波滤波器,小波滤波器的传输函数可通过对小波基函数的有理逼近获得.采用高斯函数1阶导数作为基本小波,用Padé变换获得其有理分式逼近,利用开关电流技术实现小波滤波器,并得到小波变换所需的基本小波及其膨胀小波.用Cadence Spectre对该小波滤波器进行仿真,仿真结果验证了小波滤波器的良好特性. 相似文献
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二维离散小波变换的FPGA实现 总被引:1,自引:1,他引:0
依据传统的Mallat算法,提出了一种基于FPGA实现的高速二维小波变换的方法.该方法采用模块化设计,通过将这些模块按变换要求适当级联,可轻松实现多级二维离散小波分解.用Verilog HDL实现了相关模块,并进行了仿真和逻辑综合. 相似文献
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一种新的3-D小波变换图像编码方法 总被引:2,自引:0,他引:2
基于图像序列三维小波变换的视频编码技术是一种很有潜力的编码方法.本文针对目前实际中采用的三维小波变换只是一种准三维变换,不能提供对变换结果的统一描述等不足,推导了信号真正的三维小波变换的有关理论及其实现方法.在此基础上,我们将这种三维小波变换方法用于视频图像的编码,模拟结果表明这种编码结构具有良好性能,值得进一步的深入研究. 相似文献
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提出一种基于提升算法(lifting scheme)实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.该结构由一个行处理器和一个列处理器组成,行、列处理器通过时分复用同时进行滤波,用优化的移位加操作替代乘法操作,采用嵌入式数据延拓算法处理边界延拓.整个结构采用流水线设计方法,减少了运算量,提高了硬件资源利用率,该结构可应用于JPEG2000图像编码芯片中. 相似文献
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Seung-Kwon Pack Lee-Sup Kim 《Electronics letters》1998,34(6):537-538
A cost-effective VLSI architecture with separate data-paths and their corresponding filter structure is proposed for performing a two-dimensional discrete wavelet transform (2D DWT). Compared with the conventional 2D DWT VLSI architectures, the proposed semi-recursive 2D DWT VLSI architecture has minimum hardware cost, and optimised data-bus utilisation, scheduling control overhead and storage size 相似文献
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提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100%,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N2/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中. 相似文献
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Meher P.K. Mohanty B.K. Chandra Patra J. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(2):151-155
A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages are performed concurrently for transposition-free implementation of 2-D DWT. The proposed design can offer nearly the same throughput rate, and requires the same or less the number of adders and multipliers as the best of the existing structures. The storage space is found to occupy most of the area in the existing 2-D DWT structures but the proposed structure does not require any on-chip or off-chip storage of input samples or storage/transposition of intermediate output. The proposed one, therefore, involves considerably less hardware complexity compared with the existing structures. Apart from that, it has less duration of cycle period in comparison to the existing structures, and has a latency of cycles while all the existing structures have latency of cycles, the filter order being small compared to the input size . 相似文献
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一种快速高效的二维一级小波变换的硬件实现 总被引:2,自引:1,他引:1
提出了一种针对9/7小波滤波器的二维一级小波变换的硬件平台,整体结构采用流水方式实现,数据分组输入,列变换采用多个小波变换单元,行变换模块为可重构硬件结构,行列变换之间不需要片上存储器。与已有结构相比,该结构可以通过更少的硬件资源消耗获得更高的处理速度。 相似文献
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Novel decomposed lifting scheme (DLS) is presented to perform one-dimensional (1D) discrete wavelet transform (DWT) with consistent
data flow in both row and column dimension. Based on the proposed DLS, intermediate data can be transferred seamlessly between
the column processor and the row processor in the hardware implementation of two-dimensional (2D) DWT, resulting in the reduction
of on-chip memory, output latency and control complexity. Moreover, the implementation of 2D DWT can be easily extended to
achieve higher processing speed with controlled increase of hardware cost. Memory-efficient and high-speed architectures are
proposed to implement 2D DWT for JPEG2000, which are called fast architecture (FA) and high-speed architecture (HA). FA and
HA can perform 2D DWT in N
2
/2 and N
2
/4 clock cycles for an N×N image, respectively, but the required internal memory is only 4N for 9/7 DWT and 2N for 5/3 DWT. Compared with the works reported in previous literature, the proposed designs provide excellent performance
in hardware cost, control complexity, output latency and computing time. The proposed designs were implemented to process
2D 9/7 DWT in SMIC 0.18 μm CMOS logic fabrication with 4 KB internal memory for the image size 512 × 512. The areas are only
999137 um
2
and 1333054 um
2
for FA and HA, respectively, but the operation frequency can be up to 150 MHz. 相似文献
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Hongyu Liao Mandal M.Kr. Cockburn B.F. 《Signal Processing, IEEE Transactions on》2004,52(5):1315-1326
The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures. 相似文献
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Novel architectures for 1-D and 2-D discrete wavelet transform (DWT) by using lifting schemes are presented in this paper. An embedded decimation technique is exploited to optimize the architecture for 1-D DWT, which is designed to receive an input and generate an output with the low- and high-frequency components of original data being available alternately. Based on this 1-D DWT architecture, an efficient line-based architecture for 2-D DWT is further proposed by employing parallel and pipeline techniques, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. This 2-D architecture is called fast architecture (FA) that can perform J levels of decomposition for N * N image in approximately 2N2(1 - 4(-J))/3 internal clock cycles. Moreover, another efficient generic line-based 2-D architecture is proposed by exploiting the parallelism among four subband transforms in lifting-based 2-D DWT, which can perform J levels of decomposition for N * N image in approximately N2(1 - 4(-J))/3 internal clock cycles; hence, it is called high-speed architecture. The throughput rate of the latter is increased by two times when comparing with the former 2-D architecture, but only less additional hardware cost is added. Compared with the works reported in previous literature, the proposed architectures for 2-D DWT are efficient alternatives in tradeoff among hardware cost, throughput rate, output latency and control complexity, etc. 相似文献
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Grzeszczak A. Mandal M.K. Panchanathan S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1996,4(4):421-433
This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N×106 samples/s corresponding to a clock speed of N MHz 相似文献