数字信号在不同时钟域间同步电路的设计

文中从控制信号和数据通路两个方面入手,设计了信号在不同时钟域之间的同步电路。采用直接锁存法和锁存反馈法来控制信号的跨时钟域传递,电路简洁、高效;采用异步FIFO(First In First Out)实现数据信号的同步,并通过格雷码和两级锁存来进行指针的跨时钟域传递,FIFO缓冲区的空满判断采用修改后的格雷码,对n+1位的编码可以节省(n2-n-2)/2次异或操作。该设计解决了信号跨时钟域传递时可能出现的亚稳态问题。     

FPGA设计中的跨时钟域问题

随着FPGA设计中的时钟频率越来越高,时钟方案越来越复杂,跨时钟域问题变成了设计和验证中的关键点。为了解决跨时钟域问题对FPGA设计造成功能错误,对跨时钟域信号采用两级寄存器或多级寄存器同步、握手协议和异步FIFO等同步方法;同时还提出了不检查时序、修改SDF文件和添加约束文件三种仿真中的技术,解决了跨时钟域产生的亚稳态现象对FPGA仿真验证造成的影响。     

多传感器同步图像采集系统的设计

提出了一种宽带宽、灵活的和可伸缩的多传感器同步图像采集系统的结构.设计了二进制树型拓扑结构传播统一的系统时钟和触发信号,采用CPLD提供传感器间的精确时序和同步.结构中的所有摄像机采用CMOS图像传感器采集图像.可以控制图像的尺寸、帧率以及摄像机之间的曝光顺序.为了适应不同应用对传输带宽和图像质量的不同要求,采用DSP加多种压缩算法对图像进行处理和压缩.来自所有摄像机的图像数据通过USB2.0总线采用同步传输模式传送到PC进行存储.给出了部分实现.     

基于FPGA的相机特殊时序调整系统设计

针对某型特殊时序的红外相机图像需要通过CameraLink图像采集卡进行采集并显示的工程需要,设计了基于FPGA的特殊时序调整及接口适配板卡。采用SignaTap测量红外相机的具体时序,在此基础上根据图像采集卡可以识别的时序对相机输出信号的时序进行调整。采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。采用Verilog语音编程实现有效信号的提取和无效信号的屏蔽以及行、场同步信号的调整等,将特殊时序的相机信号调整为通用CameraLink图像采集卡可以识别的信号时序。试验结果证明,经过处理的图像信号可以由CameraLink采集卡正确采集并显示,显示图像正确、稳定。     

双通道同步复装载脉冲发生方法研究

瞬态脉冲信号在工业控制、光电子通信等领域应用广泛。本文提出了一种双通道同步复装载脉冲发生方法,并基于此方法设计了一个纳秒级瞬态脉冲发生系统。该系统由时钟发生模块、双通道同步复装载计数模块和信号边沿触发模块组成。时钟发生模块输出相位相同、频率稳定的时钟信号。双通道同步复装载计数模块对生成的时钟信号进行计数并发出指示信号。指示信号通过信号边沿触发模块直接输出脉冲信号。实验结果表明：该方法可以生成脉宽可调的纳秒级脉冲信号。最小脉冲宽度和脉宽调节精度为0.833ns,与其他窄脉冲发生方法相比,脉冲宽度更窄,脉宽调节精度更高。     

一种高速数据接收同步电路的设计

介绍了一种高速数据接收同步技术,用以解决在高速、超高速情况下数据同步困难的问题.随着电路工作频率的提升,数据的稳定有效周期变得越来越短,对采样时钟的时序要求也越来越高,特别是由于工艺波动、温度变化等原因,数据与时钟的相位关系发生变化,导致时钟采样时发生误码,电路不能正常工作.采用该数据接收同步技术,可以将时钟采样设置为最佳时序,并且当时钟与数据相位关系变化时,能自动对时钟相位进行调节,重新回到最佳时序,从而大大提高数据接收的可靠性.     

MPSK数字解调器同步方案的实现

多进制相移键控MPSK调制信号的解调中,为提高解调性能,得到精确快速的载波同步和时钟同步,需要对载波检测和时钟检测作精心的设计。对MPSK的数字解调方法做了一些探讨,在载波同步中,分析了基于功率检测的频差检测方法及基于相差检测进行相位锁定的方法;详细介绍了时钟同步的波形估计方法的基本原理及幅度和频谱宽度对定时误差的影响。     

一种多路磁异常数据同步采集系统

针对金属磁性目标在掩埋情况下的定位问题,该文基于FPGA设计了一种能够同步采集24路磁场异常信号的数据采集系统;分析并解决了多组数据跨时钟域传输的问题;经过同步性测试,该文所设计的数据采集系统的同步性可以满足磁异常探测领域的要求;对金属磁性目标引起的磁场变化进行了采集,结果表明,数据采集系统可正常采集磁异常数据,为金属磁性目标的定位提供了数据基础。     

系统级芯片跨时钟域同步技术研究

随着芯片系统复杂性的提高,系统级芯片中集成了越来越多的模块,这些模块通常工作在不同的时钟频率下,这样芯片上的数据必然频繁地在不同区域之间进行传输。在时钟和数据信号从一个时钟域跨越到另一个时钟域时会发生许多类型的同步问题。采用握手信号进行异步时钟域之间的信号传输,和采用异步FIFO进行总线信号跨时钟域设计可以很好地应用在系统级芯片设计中,保证这些跨越了多个域的时钟和数据信号保持同步。     

异步时钟亚稳态仿真方法

当信号跨越时钟域的时候,会带来亚稳态问题,现在通用的做法是两级触发器同步来消除亚稳态。实际电路中在目的寄存器的时钟域获得该信号的时间可能不固定,通常相差一个时钟,提出了一种仿真方法,可以仿真实际电路中这种不确定现象。通过这种方法可以在仿真阶段检查跨时钟域信号设计是否合理。避免实际电路中的这种不稳定带来的功能失效。     

FPGA内的多时钟管理与设计

数字电路中的时钟管理和设计是一个非常重要和关键的问题,对FPGA内使用的时钟依据频率和来源提出了划分,分别讨论了它们的性质、特点和使用场合;然后探讨了不同时钟域数据传输和切换的问题,举出了使用触发器、鉴相器和FIFO缓冲解决上述问题的3种不同的方法;最后给出了一个FPGA内部使用VHDL语言设计实现多时钟15路复接器的例子。     

Distributed source-destination synchronization using inband clockdistribution

This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property     

IEEE 1588的时钟设备模型研究

IEEE 1588标准是运行在分布式测量和控制系统上,使对系统上各个节点上的独立时钟保持同步。IEEE 1588标准中定义了三种时钟设备模型,对于每一个节点,都会采用一种具体的时钟设备模型。本文就协议中的时钟模型进行分析,并对特定的网络拓扑结构采用不同的时钟模型测试,根据测试结果分析各个时钟模型在同步网络中的应用。     

Reducing clock jitter by using Muller-C elements

A simple method for reducing the cycle-to-cycle jitter of clock signals is described. The method uses Muller-C elements to merge redundant clock signals. If the two clock signals have nearly the same average phase and independently-distributed phase noise, then the jitter at the Muller-C element?s output is less than that of the input signals. This method can be used to reduce jitter in sampling clocks for analogueto- digital conversion, and in clock distribution networks for VLSI systems.     

Time-transfer performance in burst-mode communication systems

This paper studies the performance of the clock transfer scheme for burst-mode communication systems for which data are received during short, equally spaced intervals. Its main focus is on satellite-based time-division multiple-access (TDMA) communication systems with data regeneration and switching onboard the satellite, although the results apply to other TDMA systems as well. The system reference clock is generated onboard from an incoming, very stable ground source, based on a burst-mode demodulator that extracts the clock from a discontinuous modulated carrier due to the bursty nature of TDMA signals. If good enough, this onboard regenerated clock avoids the use of bulky and expensive clocks in the satellite payload and can act as the master clock of the TDMA system     

Modeling the Effect of Nonideal Reference Clocks on the Jitter Generated in Timing Transfer

In constant bit-rate timing transfer, the reference clocks which encode and reconstruct the service clock at origin and destination may be jittered. We present new, straightforward approaches to finding and visualizing jitter spectra in timing transfer for jittered destination and reference clocks, and confirm our results by simulation     

Comparing lock-in ranges and transient responses of second- and third-order phase-locked loops in master–slave clock distribution networks

The distribution of clock signals throughout the nodes of a network is essential for several applications in control and communication with the phase-locked loop (PLL) being the component for electronic synchronization process. In systems with master–slave (MS) strategies, the PLLs are the slave nodes responsible for providing reliable clocks in all nodes of the network. As PLLs have nonlinear phase detection, double-frequency terms appear and filtering becomes necessary. Imperfections in filtering process cause oscillations around the synchronous state worsening the performance of the clock distribution process. The behavior of one-way master–slave (OWMS) clock distribution networks is studied and performances of first- and second-order filter processes are compared, concerning lock-in ranges and responses to perturbations of the synchronous state.     

分相位时钟组的高速数据采样

高速的数模混合电路设计通常要求对模拟信号产生的数据进行实时准确采样。介绍了基于分相位时钟组的高速数据采样电路,并手工设计一款高性能锁相环和延时锁相环来产生数字电路时钟组,加载特定的逻辑综合约束,最终使用动态仿真工具进行电路仿真。仿真结果表明在使用分相位时钟组实现高速数据采样的同时,还可以有效地改善时序和布局布线的压力。     

Best and worst-case coverage problems for arbitrary paths in wireless sensor networks

The path-based coverage of a wireless sensor network is to analyze how well the network covers the sensor field in terms of paths. Known results prior to this research, however, considered only a single source–destination pair and thus do not provide a global outlook at the given network but a local feature for the given source–destination pair. In this paper, we propose a new coverage measure of sensor networks that considers arbitrary source–destination pairs. Our novel measure naturally extends the previous concept of the best and the worst-case path-based coverage to evaluate the coverage of a given network from a global point of view, taking arbitrary paths into account.In terms of the present coverage measure, we pose the evaluation and the deployment problems for give a network; the former is to evaluate the new coverage measure of a given sensor network, and the latter is to find an optimal placement of k additional sensor nodes to improve the coverage for a given positive integer k. We present several algorithms that are either centralized or localized that solve the problems with theoretical proofs and simulation results, thus showing that our algorithms are efficient and easy to implement in practice while the quality of their outputs is guaranteed by formal proofs. For the purpose, we show an interesting relation between the present coverage measure and a certain quantity of a point set, called the bottleneck, which has been relatively well studied in other disciplines such as computational geometry and operations research.