低噪声CMOS图像传感器的研究

近年来CMOS图像传感器在医疗和工业CT等领域中得到了越来越广泛的应用。作为CMOS图像传感器的前端处理电路,多通道积分器阵列的性能参数直接决定了传感器的成像质量并成为该领域的研究热点。本文的主要研究内容是低噪声探测器的研究。对芯片的测试结果表明,低噪声探测器的电路设计和版图设计均取得初步成功,基本达到预期的设计目标。     

应用于微小卫星的CMOS图像传感器芯片设计

针对小卫星以至微纳卫星领域的应用需求,文章对具有抗辐照能力的CMOS图像传感器的芯片架构和关键技术进行了研究,着重对行列选电路、低噪声信号读出、可编程增益放大器和片上ADC等电路设计技术进行了分析和仿真验证.基于0.35 μm CMOS抗辐照技术和工艺开展了芯片的关键电路仿真、设计和整体版图设计验证.流片后的测试结果表明,该CMOS图像传感器具有高动态、低噪声和抗辐照特点,其噪声电子为42 e-,动态范围为69 dB,当辐射总剂量大于100 krad(Si)时,器件噪声指标符合预期.     

用于CMOS图像传感器的列并行高精度ADC

设计了一种适用于CMOS图像传感器的列并行Single-slopeADC。采用的列并行ADC,同时对多数据源并行处理,增强了数据吞吐量,特别适用于CMOS图像传感器大像素阵列的数据处理。分析了影响ADC精度的因素,并给出了减小失调的方法。该ADC在0.35μm工艺下成功流片验证,测试结果表明,该ADC,在50MS/s的高数据吞吐量下,实现了CMOS图像传感器的8bit精度的设计要求和17.35mW的低功耗,以及0.62mm2的芯片面积。ADC的DNL=0.8LSB,INL=1.096LSB。     

列级反馈降低复位噪声的CMOS图像传感器

提出了一种通过放大器和开关建立起反馈环路,基于列级反馈复位的低噪声CMOS图像传感器（CIS）。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明,通过对噪声带宽与反馈放大器的带宽匹配,在复位脉冲下降沿时间为6µs的条件下,传感器的复位噪声减少25dB,满足低照度高速的安防监视系统的应用需求。     

一种基于新颖的CMOS有源像素图像传感器的微型星敏感器成像系统的实现方法

下一代星敏感器将向着小型化、低成本、低功耗的方向发展,以往的基于CCD图像传感器的成像系统由于受自身因素的制约,难以满足其发展需求.文中介绍了一种基于新颖的CMOS有源像素图像传感器的USB数字成像系统的设计实现,通过对实现的系统模型进行测试和分析,得出结论即基于CMOS有源图像传感器的成像系统完全有能力作为下一代星敏感器的光电探测器件,从而为微型星敏感器成像系统的实现提供了一种切实可行的方案.     

低噪声CMOS图像传感器的重点专利分析

随着大规模集成电路设计和信号处理技术的提高,CMOS图像传感器日益受到重视,成为固态图像传感器的研究热点,但是噪声仍是制约CMOS图像传感器发展的重要因素之一.针对低噪声的CMOS图像传感器技术领域的专利文献,给出了该领域主要申请人的申请量分布图,并对该领域的重要专利进行分析,介绍了前5位重要专利的技术特点.     

低噪声CMOS图像传感器技术研究综述

文章总结了低噪声CMOS图像传感器代表性关键技术的最新研究进展。从CMOS图像传感器架构及各模块设计的角度,介绍了有源像素结构和图像传感器架构,分析了广泛采用的像素内源跟随CMOS图像传感器读出电路及其噪声等效模型,重点介绍了低噪声CMOS图像传感器关键技术,包括共享参考像素差分共源放大器技术、相关多采样技术、像素内斩波技术,以及相关技术的电路级实现方式。     

低照度CMOS图像传感器设计与实现

设计了一种基于电容反馈跨阻放大器型（Capacitive Trans-impedance Amplifier,CTIA）像元电路与双采样（Delta Double Sampling,DDS）的低照度CMOS图像传感器系统。采用CTIA像元电路提供稳定的光电二极管偏置电压以及高注入效率,完成在低照度情况下对微弱信号的读取;同时采用数字DDS结构,通过在片外实现像元积分信号与复位信号的量化结果在数字域的减法,达到抑制CMOS图像传感器中固定图案噪声的目的,进一步提高低照度CIS的成像质量。基于0.35 m标准CMOS工艺对此基于CTIA像元电路的CMOS图像传感器芯片进行流片,像元阵列为256256,像元尺寸为16 m16 m。测试结果表明该低照度CMOS图像传感器系统可探测到0.05 lx光照条件下的信号。     

采用电荷复位技术的像素级ADC

实现了一种可用于CMOS图像传感器,采样率为50 Hz、精度为15位的像素级模数转换器(ADC)。此ADC采用电荷复位方式补偿电荷,然后通过对电荷包计数实现模数转换。为了实现低功耗、低噪声和小面积,对电路系统、核心模块的设计以及版图布局布线进行了综合考虑和优化。该设计采用SMIC 0.18μm CMOS标准工艺,版图面积为50μm×50μm。测试结果表明:当输入电流为17.5,33.7和80 nA时,对应的输出码的均值/标准差分别为8 875/6.56,16 500/2.6,32 768/14.3。在满量程输入电流(80 nA)情况下,仿真总功耗仅为4.5μW。     

一种用于CMOS图像传感器集成ADC的性能测试系统

在CMOS图像传感器中，A／D起着”承上启下”的作用，承接前端传来的信号，转换成数字后输出，其性能指标直接影响着整个系统的优劣。随着ADC速度和精度的提高，如何高效、准确地测试其动态和静态参数是ADC测试研究的重点。文中阐述了ADC的参数及其测试的原理和方法，并基于Labview软件和数据采集卡构建了ADC的软硬件测试平台．实现了低成本、高可靠性的高精度ADC计算机辅助测试系统。     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.     

A 640×512 CMOS image sensor with ultrawide dynamic rangefloating-point pixel-level ADC

Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640×512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to-digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640×512 sensor is implemented in 0.35-μm CMOS technology and achieves 10.5×10.5 μm pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed pattern noise are presented. A scene with measured dynamic range exceeding 10000:1 is sampled nine times to obtain an image with dynamic range of 65536:1. Limits on achievable dynamic range using multiple sampling are presented     

A CMOS image sensor with analog two-dimensional DCT-basedcompression circuits for one-chip cameras

This paper presents a CMOS image sensor with on-chip compression using an analog two-dimensional discrete cosine transform (2-D DCT) processor and a variable quantization level analog-to-digital converter (ADC). The analog 2-D DCT processor is essentially suitable for the on-sensor image compression, since the analog image sensor signal can be directly processed. The small and low-power nature of the analog design allows us to achieve low-power, low-cost, one-chip digital video cameras. The 8×8-point analog 2-D DCT processor is designed with fully differential switched-capacitor circuits to obtain sufficient precision for video compression purposes. An imager array has a dedicated eight-channel parallel readout scheme for direct encoding with the analog 2-D DCT processor. The variable level quantization after the 2-D DCT can be performed by the ADC at the same time. A prototype CMOS image sensor integrating these core circuits for compression is implemented based on triple-metal double-polysilicon 0.35-μm CMOS technology. Image encoding using the implemented analog 2-D DCT processor to the image captured by the sensor is successfully performed. The maximum peak signal-to-noise ratio (PSNR) is 36.7 dB     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

面阵CMOS图像传感器性能测试及图像处理

CMOS图像传感器具有驱动简单、单电源供电、集成度高、功耗低、抗辐射能力强等优点。但是在航天光学遥感领域,CMOS图像传感器应用还不普遍。在该领域亟需大规模、高读出速度、大动态范围的图像传感器,CMOS图像传感器LUPA4000正是这样一款高性能面阵图像传感器,因此,选择LUPA4000作为研究对象,对其缺陷像元、光响应非均匀性、信噪比等性能指标进行测试。测试结果表明存在缺陷像元数量多、光响应非均匀性较大、信噪比较低等问题。根据测试结果采用暗背景扣除、缺陷像元替换、非均匀校正三种方法进行图像处理。对每种方法单独处理和各种方法组合处理的处理效果从图像信噪比和成像图像质量两方面进行分析评估,结果表明:非均匀校正联合缺陷像元替换的处理方法处理效果最佳。     

An addressable 256×256 photodiode image sensor array with an 8-bit digital output

We have constructed an addressable 256 × 256 photodiode sensor array together with an 8-bit ADC (analog-to-digital converter) on the same chip. Such a digital camera is easy to connect to a computer where also the flexibility of the computer can be used to control the camera output. The sensor has been constructed in two versions. The first version was implemented with a 256-column parallel-bit-slice image processor on the same die in a commercial project and the second as a separate addressable digital image sensor. The sensor was functionally fabricated using 1.6 µm design rules in a 1.2 µm CMOS process where it required a total area of 96 mm².     

用于CMOS图像传感器的12位低功耗单斜坡模数转换器设计

 本文提出了一种应用于CMOS图像传感器中的高精度低功耗单斜坡模数转换器(single slope analog-to-digital converter)设计方案.该ADC方案由可变增益放大器、前置预放大器和动态锁存比较器组成.相比现有的设计方案,本文提出的电路在不牺牲噪声性能的前提下,具有更低的功耗和更小的芯片面积.通过集成列并行的单斜坡模数转换器在最新设计的高精度高速CMOS图像传感器设计中,实验结果证明了设计的有效性.     

A multimode digital detector readout for solid-state medicalimaging detectors

A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate ΣΔ analog-to-digital converter (ADC) to measure current over a 130-dB dynamic range in a 1 kHz band and resolve charge pulses down to 360 e^- at 100 000 events/s. Detector currents of up to 7 μA and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 μm complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm² and dissipates 11 mW/channel from a 5 V supply