2.5 Gbit/s multifunctional CMOS transceiver for chip-to-chip optical link

A novel multifunctional transceiver for chip-to-chip optical interconnects operating at 2.5 Gbit/s is proposed, which shares a common block between a receiver and a transmitter. This transceiver provides four conversion functions - electrical-to-optical, optical-to-optical, optical-to-electrical, and electrical-to-electrical - depending on the selection switch on a single chip. The whole chip integrated in 0.18 /spl mu/m CMOS occupies an area measuring 0.82/spl times/0.82 mm/sup 2/.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

49 mW 5 Gbit/s CMOS receiver for 60 GHz impulse radio

A 5 Gbit/s CMOS receiver for 60 GHz impulse radio is realised. It contains a fully differential envelope detector for differential inputs, a current mode offset canceller for robustness against PVT variations, and a high-speed comparator with hysteresis for noise immunity. The receiver is fabricated using a 90 nm CMOS process with a size of 950 x 750 spl mu/m. The total power consumption of the receiver is 49 mW at 5 Gbit/s.     

A monolithic CMOS 2368/spl plusmn/30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter

A three-pole 0.1 dB ripple Chebyshev series-C coupled resonator bandpass filter with transformer-based Q-enhancement is presented. This Q-enhancement technique compensates resonator loss and produces a flat passband response with low insertion loss. The compensation scheme uses frequency-dependent negative resistance to compensate frequency-dependent inductor losses, avoiding passband distortion, which is a problem with cross-coupled negative resistance circuits. Fabricated in 0.18 /spl mu/m CMOS, the measured filter center frequency is 2368 MHz with a 60 MHz (3 dB) bandwidth, including probe pad and connecting trace parasitic losses. The filter draws 5.84 mA at 1.5 V, and the die area is 1.5 mm/spl times/1.5 mm.     

A 2-Gb/s 0.5-/spl mu/m CMOS parallel optical transceiver with fast power-on capability

This paper describes an optical transceiver designed for power-efficient connections within high-speed digital systems, specifically for board- and backplane-level interconnections. A 2-Gb/s, four-channel, dc-coupled differential optical transceiver was fabricated in a 0.5-/spl mu/m complementary metal-oxide-semiconductor (CMOS) silicon-on-sapphire (SoS) process and incorporates fast individual-channel power-down and power-on functions. A dynamic sleep transistor technique is used to turn off transceiver circuits and optical devices during power-down. Differential signaling (using two optical channels per signal) enables self-thresholding and allows the transceiver to quickly return from power-down to normal operation. A free-space optical link system was built to evaluate transceiver performance. Experimental results show power-down and power-on transition times to be within a few nanoseconds. Crosstalk measurements show that these transitions do not significantly impact signal integrity of adjacent active channels.     

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-/spl mu/m CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10/sup -12/ while consuming 540 mW from a 1.8-V supply.     

A 2.4-GHz dual-mode 0.18-/spl mu/m CMOS transceiver for Bluetooth and 802.11b

High-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-/spl mu/m CMOS occupies 4/spl times/4 mm/sup 2/ including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.     

A 2.4-GHz 0.25-/spl mu/m CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b

A dual-mode transceiver integrates the transmitter of 0-dBm output power and the receiver for both Bluetooth with -87 dBm sensitivity and 802.11b with -86 dBm sensitivity in a single chip. A direct-conversion architecture enables the maximum reuse and the optimal current consumption of the various building blocks in each mode for a low-cost and low-power solution. A single-ended power-amplifer (PA) driver transmits the nominal output power of 0 dBm with 18-dB gain control in 3-dB steps. Only little area overhead is required in the baseband active filter and programmable gain amplifier (PGA) to provide the dual-mode capability with optimized current consumption. The DC-offset cancellation scheme coupled with PGAs implements the very low high-pass cutoff frequency with a smaller area than required by a simple coupling capacitor. Fabricated in 0.25-/spl mu/m CMOS process, the die area is 8.4 mm/sup 2/ including pads, and current consumption in RX is 50 mA for Bluetooth and 65 mA for 802.11b from a 2.7-V supply.     

A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-/spl mu/m CMOS

A divide-by-16.5 frequency divider, providing read- and write-clocks for an elastic buffer or a gearbox between 10.3125-Gb/s and quad 3.125-Gb/s transceivers in 10-G Ethernet application, is presented. The high-speed and noninteger division is designed by cascading high-speed divide-by-3 followed by divide-by-5.5 which uses double-edge-triggered flip-flops. The divide-by-3 circuit receives and generates 5.15625-GHz and 1.71875-GHz differential clocks with a 50% duty cycle, respectively. Based on current-mode logics (CMLs), the proposed divide-by-16.5 scheme is implemented in a 0.13-/spl mu/m CMOS technology to achieve over 5-GHz operation while consuming 18 mW from a 1.2-V supply.     

A 0.13-/spl mu/m CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer

The frequency-dependent attenuation of the transmission lines between chips and printed circuit boards, for example, is an obstacle to improving the performance of a system enhanced with LSI technology scaling. This is because large frequency-dependent attenuation results in poor eye-opening performance and a high bit-error rate in data transmission. This paper presents a 5-Gb/s 10-m 28AWG cable transceiver fabricated by using 0.13-/spl mu/m CMOS technology. In this transceiver, a continuous-time post-equalizer, with recently developed no-feedback-loop high-speed analog amplifiers, can handle up to 9dB of frequency-dependent attenuation in cables and also achieve an 18-dB improvement in the attenuation (27dB total improvement) by using pre- and post-equalization techniques in combination.     

A novel multi-antenna impulse radio UWB transceiver for broadband high-throughput 4G WLANs

In the last years, a lot of attention has been devoted to both multi-antenna systems with space-time orthogonal block coding (STOBC) and ultra wideband (UWB) transceivers based on impulse-radio (IR) technologies. In this short contribution we anticipate the architecture of a novel transceiver merging both multi-antenna and pulse position modulation (PPM) IR-UWB techniques and then we test the performance in flat-faded application scenarios typical of emerging broadband 4G WLANs. Three main appealing features are retained by the sketched transceiver scheme. First, it allows to equip the UWB receiver with reliable estimates of the (possibly time-varying) underlying multiple-input multiple-output (MIMO) UWB without reducing the overall information throughput conveyed by the system. Second, the performance confirms that the proposed transceiver is able to achieve "full diversity" even at SNRs as low as 1.5-2 dB. As a consequence, the resulting BERs outperform those of current Single-Input Single-Output (SISO) IR-UWB transceivers over two orders of magnitude even at SNR's as low as 3-4 dB. Third, at target BER's below 10/sup -2/ and radiated powers around 250 /spl mu/W, the coverage ranges allowed by the proposed MIMO IR-UWB scheme typically outperform those of conventional SISO IR-UWB ones of about two orders of magnitude.     

A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-/spl mu/m CMOS

A fully integrated transceiver suitable for low-data-rate wireless telemetry and sensor networks operating in the license-free ISM frequency bands at 433, 868, or 915 MHz implemented in 0.25-/spl mu/m CMOS is presented. G/FSK, ASK, and OOK modulation formats are supported at data rates from 0.3 to 200 kb/s. The transceiver's analog building blocks include a low-noise amplifier, mixer, channel filter, received signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. FSK demodulation is implemented using a novel digital complex-frequency correlator that operates over a wide modulation-index range and approximates matched filter detection performance. Automatic gain control, automatic frequency control, and symbol timing recovery loops are included on chip. Operating in the 915-MHz band in FSK mode at 9.6 kb/s, the receiver consumes 19.7 mA from a 3-V supply and achieves a sensitivity of -112.8dBm at 0.1% BER. The transmitter consumes 28.5 mA for an output power of 10 dBm and delivers up to 14 dBm.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-/spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps/sub rms/ and 9.67 ps/sub pp/ with a PRBS of 2/sup 31/-1 while consuming 144 mW from a 2-V supply.     

A 0.18 μm CMOS transimpedance amplifier with 26 dB dynamic range at 2.5 Gb/s

A new transimpedance amplifier (TIA) for 2.5 Gb/s optical communications fabricated in a standard 0.18 μm CMOS process is presented. The proposed TIA is based on a conventional structure with an inverting voltage amplifier and a feedback resistor, but incorporates a new technique to enhance the input dynamic range and to prevent the TIA from saturation at high input currents. According to electrical characterization the receiver shows an optical sensitivity of −26 dB m for a BER=10⁻¹², assuming a responsivity of 1 A/W, and an optical power dynamic range above 26 dB. The power consumption of the core is only 10.6 mW at a single supply voltage of 1.8 V.     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A 15-gb/s 2:1 multiplexer in 0.18-/spl mu/m CMOS

By employing the inductive peaking technique and the super-dynamic flip-flops, a 2:1 multiplexer (MUX) is presented for high-speed operations. The proposed circuit is realized in a 0.18-/spl mu/m CMOS process. With a power consumption of 110mW from a 2-V supply voltage, the fully integrated MUX can operate at an output rate up to 15Gb/s. From the measured eye-diagrams, the 15-Gb/s half-rate MUX exhibits an output voltage swing of 225mV and a root-mean-square jitter of 2.7ps.     

A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 /spl mu/s offset compensation

A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain, bandwidth, power dissipation, and noise performance of the limit amplifier are discussed. Measured results of a custom 3.125 Gb/s limit amplifier in 0.18 /spl mu/m CMOS employing the proposed compensation technique demonstrate a sub-1-ms settling time while still achieving less than 4 ps rms output jitter with a 2.5 mV peak-to-peak input at 2.5 Gb/s.