Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Reduction of crosstalk noise in modular jack for high-speeddifferential signal interconnection

Crosstalk noise has become a significant problem in the design of high-speed digital interconnections. In this paper, we demonstrate a crosstalk reduction method, which has been successfully applied to the design of a CAT-5E modular jack. The CAT-5E is a newly adopted cabling and connector standard for advanced cabling network systems to assure more robust, reliable and high-speed operation, which is based on differential mode signal transmission using unshielded twist pair (UTP) cable. The improved design of the modular jack shows minimal crosstalk noise and return loss over a wide range of manufacturing conditions. The improved crosstalk characteristics of the modular jack were accomplished by inserting embedded capacitors on the printed circuit board (PCB) of the modular jack. The embedded capacitors compensate for the unbalanced capacitive crosstalk that occurs in the plug and insert. In particular, the embedded balancing capacitor is designed to have maximum capacitance, with limited PCB area, by using a double-sided PCB design. Less than -45 dB near-end-crosstalk (NEXT) was achieved after the crosstalk noise compensation, satisfying the CAT-5E specification for frequencies up to 100 MHz     

RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic Substrates by Wafer-Transfer Technology (WTT) for System-on-Package Applications

In this paper, radio frequency (RF), dc, and reliability performance have been studied on metal-insulator-metal (MIM) capacitors embedded in organic substrates. The MIM structure including ~74-nm SiN dielectric was prefabricated on Si and then transferred onto organic substrates (FR-4) by wafer-transfer technology (WTT). The RF characteristics up to 30 GHz were investigated by equivalent lumped circuit modeling, showing that the parameters associated with the MIM layers including the main capacitance, parasitic inductance, and resistance were only slightly changed by the WTT process. The substrate-related parasitics were reduced as a result of the replacement of lossy Si with insulating FR-4 substrates. Excellent capacitance linearity, low voltage coefficient (~2.2 ppm/V²), and temperature coefficient (~38 ppm/degC) were obtained for capacitors on FR-4 substrates. Current-voltage and time-dependent dielectric breakdown tests verified that, after the harsh processes of WTT, the MIM structures maintained the intrinsic reliability as those originally fabricated on Si. This paper, along with earlier reports, proved that WTT presented a new dimension to realize embedded capacitors for high-density circuit board and system-on-package applications     

Improving the Characteristics of integrated EMI filters by embedded conductive Layers

Discrete electromagnetic interference (EMI) filters have been used for power electronics converters to attenuate switching noise and meet EMI standards for many years. Because of the unavoidable structural parasitic parameters of the discrete filter components, such as equivalent parallel capacitance (EPC) of inductors and equivalent series inductance (ESL) of capacitors, the effective frequency range of the discrete filter is normally limited. Aiming at improving high frequency performance and reducing size and profile, the integrated EMI filter structure has been proposed based on advanced integration and packaging technologies , . Some improvements have been made but further progress is limited by EPCs of the filter inductors, which is restricted by dimension, size and physical structure. In this paper, a new structural winding capacitance cancellation method for inductors is proposed. Other than trying to reduce EPCs, a conductive ground layer is embedded in the planar inductor windings and the structural capacitance between the inductor winding and this embedded layer is utilized to cancel the parasitic winding capacitance. In order to obtain the best cancellation effect, the structural winding capacitance model of the planar spiral winding structure is given and the equivalent circuit is derived. The design methodology of the layout and area of the embedded ground layer is presented. Applying this method, an improved integrated EMI filter is designed and constructed. The experimental results show that the embedded conductive layer can effectively cancel the parasitic winding capacitance, hence ideal inductor characteristics can be obtained. With the help of this embedded conductive layer, the improved EMI filter has much smaller volume and profile and much better characteristics over a wide frequency range, compared to the former integrated EMI filter and the discrete EMI filter.     

Embedded Capacitors in Printed Wiring Board: A Technological Review

This paper reviews the technology of embedded capacitors, which has gained importance with an increase in the operating frequency and a decrease in the supply voltage of electronic circuits. These capacitors have been found to reduce the number of surface-mount capacitors, which can assist in the miniaturization of printed wiring boards. This paper describes various aspects of embedded capacitors, such as electrical performance, available dielectric materials, manufacturing processes, and reliability. Improvement in electrical performance is explained using a cavity model from the theory of microstrip antennas. The advantages and disadvantages of dielectric materials such as polymers, ceramics, polymer–ceramic composites, and polymer–conductive filler composites are discussed. Various manufacturing techniques that can be used for the fabrication of embedded capacitors are also discussed. Embedded capacitors have many advantages, but failure of an embedded capacitor can lead to board failure since these capacitors are not reworkable. The effect of various environmental stress conditions on the reliability of embedded capacitors is reviewed.     

Application-specific economic analysis of integral passives inprinted circuit boards

This paper presents an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. In this study we assume that integral resistors are printed or plated directly onto wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors, if present, are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors, if present, are embedded using dedicated layer pair addition. The model presented performs three basic analyses. 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel. 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels. 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost tradeoffs for several example systems including the NEMI hand-held emulator, a picocell board, and a fiber channel card     

Embedded resistors and capacitors for organic-based SOP

System-on-package (SOP) architectures take advantage of compact, high-performance designs to place the maximum amount of functionality on a subsystem that can then be mounted on a lower-cost, lower density interconnect board. Embedding passive components is a key technology in achieving these goals since this enables smaller SOP substrate footprints or, equivalently, higher functional density, along with better power distribution, increased design flexibility and improved reliability. The resulting footprint areas of integrating capacitors will have more of an effect on the layer count of SOP assemblies than will integrating resistors due to the rather low specific capacitances of most embeddable dielectrics, but the situation is improving steadily. It may be necessary to use two different dielectric materials to cover the entire required range. The inherently lower parasitic inductance of embedded capacitors makes them much more useful in decoupling than surface mount capacitors, enabling more robust power distribution and decreased power/ground noise. The key to this performance enhancement in large boards is the use of a thin dielectric to decrease the inductance but, for the smaller SOP substrates, the dielectric constant must also be high to provide sufficient decoupling capacitance in the reduced area.     

埋置电容板板边分层探究和改良

针对埋容板板边分层问题,通过分析并跟进埋容板生产各关键制程,确认了埋容板板边分层的原因。受机械应力作用时铜层与埋容材料层之间出现微小裂纹,随着机械应力作用次数的增加,裂纹扩展导致分层。通过试验验证,更改了埋容层芯板的制作照相底片,彻底解决了埋容板板边分层的问题。     

Planar lightwave integrated circuits with embedded actives for board and substrate level optical signal distribution

This paper explores design options for planar optical interconnections integrated onto boards, discusses fabrication options for both beam turning and embedded interconnections to optoelectronic devices, describes integration processes for creating embedded planar optical interconnections, and discusses measurement results for a number of integration schemes that have been demonstrated by the authors. In the area of optical interconnections with beams coupled to and from the board, the topics covered include integrated metal-coated polymer mirrors and volume holographic gratings for optical beam turning perpendicular to the board. Optical interconnections that utilize active thin film (approximately 1-5 /spl mu/m thick) optoelectronic components embedded in the board are also discussed, using both Si and high temperature FR-4 substrates. Both direct and evanescent coupling of optical signals into and out of the waveguide are discussed using embedded optical lasers and photodetectors.     

High Density Double and Triple Layer Tantalum Pentoxide Decoupling Capacitors

High-performance integrated circuits (ICs) require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area tantalum pentoxide (TaO) dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to 100nF/cm for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. We previously described the initial results of two-layer capacitors fabricated on silicon . These devices had two dielectric layers and three copper plates. Recently we extended the technology to three dielectric layers, and fabricated devices with dielectrics as thin as 1000, to yield a total capacitance density of 0.6F/cm. Capacitors were fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process was repeated to create a multilayer stack. The stack was then patterned from top to bottom by successive lithographic and etching steps. This paper will describe the fabrication process in detail. Detailed electrical properties for the resulting two and three layer devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices will be described. Screening and test methods to ensure device reliability will be briefly discussed.     

Optimizing Embedded Passive Content in Printed Circuit Boards

A genetic algorithm's optimization approach is used in conjunction with a size/cost model to study the optimum mix of passives (resistors and capacitors) to embed within a printed circuit board on an application-specific basis. Using the models and solution approach developed in this paper, the effect of board size on the optimum embedded passive solution (minimum cost solution) is studied, and an assessment of whether better system solutions can be found by varying or constraining the size of the board using several different criteria has been performed. Example optimization results for a GSM mobile phone are presented. The analysis has shown that the system size limitation when embedded passives are used is not only dependent on the quantity, type, and electrical properties (capacitance and resistance) of the embeddable components, but is also very sensitive to layout specifications and the placement of the nonembeddable parts.     

以太网通信在网络化测试中的实现

文章详细介绍了网络化测试的一个基本通信技术----以太网通信技术的研究和实现。使用INTEL386EX设计一块以太网通信测试单板NCEX,使用C语言实现一个在该单板上运行的嵌入式TCP/IP协议栈,单板成为UDP服务器;并使用Visual C＋＋ 6.0的Socket功能在计算机上设计UDP客户端,实现多台计算机通过以太网和UDP/IP协议与NCEX测试板同时通信。     

Environmental Qualification Testing and Failure Analysis of Embedded Resistors

Embedding passive components (capacitors, resistors, and inductors) within printed wiring boards (PWBs) is one of a series of technology advances enabling performance increases, size and weight reductions, and potentially economic advantages in electronic systems. This paper explores the reliability testing and subsequent failure analysis for laser-trimmed Gould subtractive nickel chromium and MacDermid additive nickel phosphorous embedded resistor technologies within a PWB. Laser-trimmed resistors that have been “reworked” using an inkjet printing process to add material to their surface to reduce resistance have also been considered. Environmental qualification testing performed included: thermal characterization, stabilization bake, temperature cycling, thermal shock and temperature/humidity aging. In addition, a pre/post-lamination analysis was performed to determine the effects of the board manufacturing process on the embedded resistors. A failure analysis consisting of optical inspection, scanning acoustic microscope (SAM) and environmental scanning electron microscope (ESEM) imaging, and PWB cross-sectioning was employed to determine failure mechanisms. All the embedded resistors were trimmed and the test samples included resistors fabricated both parallel and perpendicular to the weave of the board dielectric material. Material stability assessment and a comparison with discrete resistor technologies was performed.     

Analysis of the bounces on the power/ground plane structures byplanar circuit model and APA-E algorithm

In this paper, a novel effective numerical algorithm for analysis of the bounces on the power/ground-plane structure in printed circuit board (PCB) or multichip modules (MCMs) is proposed, which is based upon planar circuit model combined with APA-E algorithm. Firstly, the planar circuit model is developed to simulate the power/ground bounces when switching current is added in the structure. Secondly, on the basis of the abstract Pade approximant and the extrapolation algorithm, the APA-E algorithm is proposed. The classical multivariable rational Pade approximant is also constructed for comparison. Compared with finite difference time domain (FDTD) method, the new algorithm can provide a very accurate approximant in time domain, only requires little storage and CPU time. At last, attaching the decoupling capacitors for reducing the bounces on lossy power/ground-plane structures is also analyzed with this method     

Novel Integration of Metal–Insulator–Metal (MIM) Capacitors Comprising Perovskite-type Dielectric and Cu Bottom Electrode on Low-Temperature Packaging Substrates

In this letter, a novel integration scheme, for metal-insulator-metal capacitors comprising perovskite-type dielectrics and Cu-based bottom electrodes, has been demonstrated on low-temperature FR4 packaging substrates. Cu oxidation during dielectric deposition and postannealing is completely avoided by a dielectric-first process flow with Ti as oxygen-getter. By using evaporated barium strontium titanate as capacitor dielectric, a maximum capacitance density (~1250 nF/cm² at 100 kHz) and moderate leakage current (< 4 times 10^-5 A/cm² at 2 V) have been achieved with rapid thermal annealing at 700degC. Higher temperature leads to dielectric degradation. Combined with advanced deposition techniques, this integration scheme enables realization of high-performance embedded capacitors that can be integrated with printed circuit board technology.     

Compensating for moderate effective throughput at the desktop

This article presents the design and development of a networking system architecture targeted to support high-speed TCP/IP communication over ATM. The discussed architecture has been developed in the form of an integrated system which incorporates state-of-the-art software and hardware subsystems, and an OC-12c ATM adapter (622 Mb/s). Moreover, the design of this embedded system has been based on the Chorus real-time operating system, which, in turn, hosts an accelerated TCP/IP protocol stack over ATM. Furthermore, the embedded system board has been developed according to the PCI specification to easily be plugged into a host platform. In addition, the OC-12c ATM adapter subsystem has been designed and developed in order to also be plugged into the same host. The developed architecture has proven very efficient and reliable, providing high-throughput and low-latency bulk data communications. The measured performance on an OC-3c-based (155 Mb/s) testbed has shown that an optimally implemented TCP/IP stack, hosted by a real-time kernel and coupled with an ATM adapter, offers a robust desktop platform for high-speed end-to-end communications. The main feature of the accelerated TCP/IP protocol stack is the out-of-band processing of control and data information. The protocol accelerator embedded system processes the TCP/IP headers and accomplishes checksum computations, while data is transferred from the host's user memory space directly to the network. Finally, for validation purposes, the prototype system has been incorporated in an existing networking infrastructure targeted to support mass storage applications     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate

The low-frequency noise of silicon pMOSFETs with embedded SiGe source/drain (S/D) regions is studied. The gate stack consists of HfSiON/SiO₂ covered by a fully silicided gate electrode. S/D regions with different Ge content and thickness have been processed. It is shown that, while mobility and drive current are significantly enhanced by this strain-engineering approach, the 1/f noise is little affected, irrespective of the germanium content or thickness of the epitaxial SiGe S/D layers, i.e., the amount of compressive strain in the channel. From this, it is derived that, first of all, the embedded (S/D) processing does not degrade the gate-stack quality and that, second, no evidence of an intrinsic strain effect on the 1/f noise is observed here.     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

Optimization of Epoxy-Barium Titanate Nanocomposites for High Performance Embedded Capacitor Components

One of the most promising avenues to meet the requirements of higher performance, lower cost, and smaller size in electronic systems is the embedded capacitor technology. Polymer-ceramic nanocomposites can combine the low cost, low temperature processability of polymers with the desirable electrical and dielectric properties of ceramic fillers, and have been identified as the major dielectric materials for embedded capacitors. However, the demanding requirements of mechanical properties and reliability of embedded capacitor components restrict the maximum applicable filler loading (<50vol%) of nanocomposites and thereby limit their highest dielectric constants (<50) for real applications. In this paper, we present a study on the optimization of the epoxy-barium titanate nanocomposites in order to obtain high performance, reliable embedded capacitor components. To improve the reliability of polymer-ceramic nanocomposites at a high filler loading, the epoxy matrix was modified with a secondary rubberized epoxy, which formed isolated flexible domains (island) in the continuous primary epoxy phase (sea). The effects of sea-island structure on the thermal mechanical properties, adhesion, and thermal stress reliability of embedded capacitors were systematically evaluated. The optimized, rubberized nanocomposite formulations had a high dielectric constant above 50 and successfully passed the stringent thermal stress reliability test. A high breakdown voltage of 89MV/m and a low leakage current of about 1.9times10^-11A/cm² were measured in the large area thin film capacitors