Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

A 14-b, 100-MS/s CMOS DAC designed for spectral performance

A 14-bit, 100-MS/s CMOS digital-to-analog converter (DAC) designed for spectral performance corresponding more closely to the 14-bit specification than current implementations is presented. This DAC utilizes a nonlinearity-reducing output stage to achieve low output harmonic distortion. The output stage implements a return-to-zero (RZ) action, which tracks the DAC once it has settled and then returns to zero. This RZ circuit is designed so that the resulting RZ waveform exhibits high dynamic linearity. It also avoids the use of a hold capacitor and output buffer as in conventional track/hold circuits. At 60 MS/s, DAC spurious-free dynamic range is 80 dB for 5.1-MHz input signals and is down only to 75 dB for 25.5-MHz input signals. The chip is implemented in a 0.8-μm CMOS process, occupies 3.69×3.91 mm ² of die area, and consumes 750 mW at 5-V power supply and 100-MS/s clock speed     

Design of a 100-MHz 10-mW 3-V sample-and-hold amplifier in digitalbipolar technology

This paper describes the design of an all-npn open-loop sample-and-hold amplifier intended for use at the front end of analog-to-digital converters. Configured as a quasidifferential topology, the circuit employs capacitive coupling between the input and output to achieve differential voltage swings of 3 V in a 3.3-V system. It also exploits the high speed of bipolar transistors to attain a sampling rate of 100 MHz with a power dissipation of 10 mW. A prototype fabricated in a 1.5-μm 12-GHz digital bipolar technology exhibits harmonics 60 dB below the fundamental with a 10-MHz sinusoidal input. The hold-mode feedthrough is less than -60 dB and the droop rate is 100 μV/ns     

Digital-compatible high-performance operational amplifier withrail-to-rail input and output ranges

This paper presents a CMOS buffer amplifier which operates on a single 5-V power supply. The uniquely symmetrical design adds the following advantages: rail-to-rail linear, symmetrical operation at both the input and output; the output stage allows the use of gate channel capacitors of standard MOSFET's as the compensation capacitor saving die area from 80%~93% in a standard single polysilicon digital process; large gain-bandwidth product; high power supply rejection ratio; good common-mode rejection ratio; and easy compact layout suitable for design automation (layout as a parametric cell, allows easy adaption to changing processes). The buffer is capable of driving 300 Ω∥100 pF with a loaded gain-bandwidth product of more than 4 MHz and a fully loaded slew rate of greater than 4 V/μS     

A wide-band, low-power, high slew rate voltage-feedback operationalamplifier

A wide-band low-power voltage-feedback operational amplifier on a 3 GHz, 40 V complementary bipolar technology is described. The class AB input stage takes advantage of some current-boost transistors which enhance and linearize the slew-rate during large-signal operation without increasing the power consumption. The triple-buffered output stage provides 100 mA of load current maintaining good linearity. Since the circuit design and technology development were concurrent, several different circuits were stepped into one wafer to fully characterize the process and identify the best product candidates. The low-current version of this chip has a quiescent current of 2.5 mA, 2000 V/μs slew rate and gain bandwidth of 110 MHz. The medium-current version draws only 6.5 mA of current at the same supply voltage while the slew rate increases to 3500 V/μs and bandwidth to 210 MHz. Both parts are operational from +/-2.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process     

A high slew-rate unity-gain low-voltage buffer with largeactive/quiescent current ratio

A buffer that can source or sink up to 10 mA with a slew rate of 130 V/μs in a series RC load of 500 Ω and 12 nF is introduced. The buffer has a standby current of 400 μA which is reduced to 50 nA in less than 100 ns in power-down mode. It operates with a 2.7-V supply and is designed for personal communications applications such as Digital Enhanced Cordless Telecommunications (DECT). The adaptive biasing technique employed in this design makes it suitable for other applications like high-speed sample-and-hold or transconductance stages     

A high temperature precision amplifier

A precision operational amplifier has been developed for instrumentation applications in which the circuitry must operate in ambient temperatures as high as 200°C. At 200°C the amplifier maintains an input offset voltage and current of less than 200 μV and 1 nA respectively, a gain bandwidth product of 2.2 MHz, and a slew rate of 5.4 V/μS. The amplifier is fabricated in a standard CMOS process and consumes 5.5 mW of power at a supply voltage of 5 V. A continuous time auto-zeroed amplifier topology is used to achieve the low offset voltage levels. At high temperatures the leakage currents of the sample and hold switches used to achieve auto-zeroing, degrading the offset correction voltages stored on the hold capacitors. This degradation is reduced by using large external hold capacitors and by minimizing the diffusion area of the switches through the use of a doughnut shaped layout. The effect of the voltage degradation is reduced by sensing the offset correction voltage with a low sensitivity differential auxiliary input stage. A new input switch topology is used to reduce the amplifier's input offset current at high temperatures     

A rail-to-rail, constant gain, buffered op-amp for real time videoapplications

Inspired by Hogervorst et al's current switch idea, a buffered output stage operational amplifier was designed, which has high frequency, high dc gain, and rail-to-rail constant transconductance (G _m). This operational amplifier is the output stage of an analog/digital system which implements a Gabor convolution for real-time dynamic image processing and it is designed to interface the external analog-to-digital converter (ADC) with a very heavy load. The op amp was fabricated by the MOSIS service in a 2-μm, n-well CMOS, double polysilicon, double metal technology. The fabricated circuit operates from a single 5 V power supply and dissipates 10 mW. The open loop-gain of the fabricated circuit, A_vol, was measured as 67.2 dB for a 163 Ω∥33 pF load. Other dc and ac characteristics were measured for a 50 Ω∥33 pF load. The unify gain-bandwidth (GBW) was measured to be 11.4 MHz, the rising slew rate (SR+) 20.4 V/μs, the falling slew rate (SR-) 18.8 V/μs, and the offset voltage (V_off) 1 mV. The output swings with an amplitude of 3.24 V between 0.88 V and 4.12 V, which matches the input signal specifications of the ADC. In addition to rail-to-rail output voltage swing, the opamp has a constant G_m over the whole common mode (CM) voltage range     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

A constant-g_m and high-slew-rate operational amplifier for an LCD driver

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gin input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the gm of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm~2. The testing results indicate that in the 5-8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μsand 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to109 dB with a phase margin of 70 ℃.     

A low noise compact class AB buffer amplifier with accurate quiescent current control

The authors present a new low-noise class AB buffer amplifier. The proposed buffer amplifier achieves a low noise with fast settling time and low power consumption. The buffer amplifier circuit attains an input referred noise voltage of 12.8 \( {{\text{nV}} /{\sqrt {\text{Hz}}}} \), a DC gain of 108 dB, a unit-gain frequency of 8 MHz, and rising slew rate of 36 V/μs, as the load capacitance equals 150 pF. The circuit is power efficient when driving large capacitive loads and is well suited for low noise low power analog video buffer applications.     

110-GB/s simultaneous bidirectional transceiver logic synchronizedwith a system clock

A simultaneous bidirectional transceiver logic (SBTL), for a 0.25 μm CMOS embedded array, has a low-voltage-swing input flip-flop circuit and an output flip-flop with a boundary scan to enable a 1.1-Gb/s data transfer per LSI pin with a 550-MHz system clock. Clock skew and jitter minimization enables high bandwidth in a phase-locked system. Measured latency time for transmission is less than 3.0 ns during simultaneous switching mode when the cable length is 18 cm. Average power consumption is 12 mW per pin at 550 MHz. A low-noise output buffer and a controlled collapse chip connection (C4)-based 1595-pin package with on-package capacitors achieve 100-byte data bus. The maximum data bandwidth per LSI is 110 GB/s     

A compact low noise operational amplifier for a 1.2 μm digitalCMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm² with E_n=3.2 nV/√(Hz), I_n=0.73 pA/√(Hz), E_n and I_n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs     

可编程输入输出接口设计研究

针对输入输出接口设计中多电平标准兼容,宽输入输出电压范围,多驱动调节,翻转率控制,以及高速接口中信号反射等问题,提出一个易于扩展的可编程接口设计方案。实现了一个用于现场可编程门阵列（FPGA）的可编程输入输出接口,通过编程可实现多达16种接口电平标准,兼容5V电压的,TTL电平。测试结果表明,接口速度和国外同类产品接近,静态电流优于国外的同类产品。     

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design     

A 3-V 5.4-mW BiCMOS track & hold circuit with samplingfrequency up to 150 MHz

A track & hold circuit to be used in front of a high-speed analog-to-digital converter (ADC) is proposed. In order to achieve the required resolution with a single 3-V supply, a fully differential closed-loop architecture is used. The track & hold circuit processes a differential 1-Vpp output signal swing and achieves more than 8-b linearity with sampling frequency up to 150 MHz. In these conditions, the total power consumption is 5.4 mW from a single 3-V supply. The circuit has been realized in a 0.7 μm BiCMOS technology, and its active area is about 0.15 mm²     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

一种高转换速率衬底电位选择电路的设计

本文基于0.5μm 5V DPTM CMOS工艺设计了一款用于LED驱动芯片的衬底电位选择电路。该电路采用峰值电流镜作为偏置,使其在低电压下能够正常工作,并运用源端输入带正反馈的比较器,使得电路具有一定的迟滞和高的转换速率,最后巧妙的设计了输出级,使输出结果尽可能的与芯片中的最高电压相等。仿真结果显示,比较器的转换速率为55.7V/μs,并且具有0.2V的迟滞,满足设计要求。