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1.
This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm2 using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V  相似文献   

2.
A 4096-bit ECL random-access memory using high-density I2L memory cell has been developed. Novel ECL circuit techniques and I2L flip-flop memory cells are introduced for realizing high-speed performance, low-power operation, and small chip size. It operates typically under 20-ns access time and 300 mW of power dissipation, realizing 1.46 pJ/bit of access time and power-per-bit product, a figure of merit of memory devices. The memory cell and chip size of 1122 µm2(33 µm × 34 µm) and 9.9 mm2(3 mm × 3.3 mm), respectively, are achieved with V-groove isolated bipolar process technology. The memory is organized into 4096 words × 1 bit, and is packaged into 18-pin DIP and also 18-pad leadless chip carrier package. Development results have shown that the n-p-n-coupled superintegrated I2L flip-flop memory cell is very promising for high-speed and low-power static RAM's above 4K-bit/chip area.  相似文献   

3.
The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure  相似文献   

4.
This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 μm2 and a die size of 42.9 mm2 have been achieved with 0.8 μm design rules. Read access time and search access time are 115 ns and 135 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access  相似文献   

5.
This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil2and the total chip size is 218 × 235 mil2. The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.  相似文献   

6.
A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm2 is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M×16-b configuration dissipates 60 mA at 3.6 V  相似文献   

7.
A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm2 and the chip size is 4.38×9.47 mm 2  相似文献   

8.
An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm2, and the chip area is 12.7×16.91 mm2  相似文献   

9.
A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm2 in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm2 to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time  相似文献   

10.
A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm2  相似文献   

11.
This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-μm ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25°C, 110-ns minimum cycle. The die size is 116 mm2 using 9 μm2, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology  相似文献   

12.
This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot-electron (CHE) programmed flash memory fabricated in 0.18-μm shallow-trench isolation CMOS technology. The device (die size 40 mm2) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window. Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated  相似文献   

13.
An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm2, using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm2, which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved  相似文献   

14.
4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm2. Cell size is 278 μm 2 at 1.0-μm gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm2. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA  相似文献   

15.
We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm2 memory cell. The macro size of the LL4T-SRAM is 56 mm2, which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell  相似文献   

16.
A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm2 and the chip size is 11×11 mm  相似文献   

17.
A nonvolatile chain FRAM adopting a new cell-plate-line drive technique was demonstrated. Two key circuit techniques, a two-way metal cell-plate line and a cell-plate line shared with 16 cells, reduce cell-plate-line delay to 7 ns and reduce plate drive area to 1/5. The total cell-plate-line delay, including cell transistor delay due to eight cells in series, is reduced to 15 μs, in contrast to 30-100-ns delay of the conventional FRAM. The die size is reduced to 86% that of the conventional FRAM by reduction of the plate driver area and sense amplifier area, assuming the same memory cell size. A prototype 16-kb chain FRAM chip was fabricated using 0.5 μm rule one-polycide and two-metal CMOS process. The memory cell size was 13.26 μm2 using a 3.24-μm2 capacitor. Thanks to the fast cell-plate-line drive, the chain FRAM test chip has achieved the fastest random access time, 37 ns, and read/write cycle time, 80 ns, at 3.3 V so far reported. The chain FRAM has also realized Vdd min of 2.3 V and 1010 read/write cycles  相似文献   

18.
A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm2 is fabricated and an address access time of 12.5 ns has been achieved  相似文献   

19.
A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm2 cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm2  相似文献   

20.
A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25-μm CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 μm2. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm2  相似文献   

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