Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Effects of electric fields on annealing of radiation damage in MOSFET's

Radiation damage inp-channel MOS devices by 1.5 MeV electrons has been studied by thermal annealing in conjunction with electric fields between the metallic gate and the substrate. Both positive and negative gate biases retard the process of annealing. Annealing with negative gate bias reveals 1) that during thermal annealing the majority of the electrons that recombine with the positive charge in the oxide originate from the conduction band of the silicon, and 2) that during irradiation a great number of ionized electrons that remain in the oxide do not recombine with the holes, but are trapped in weakly bound states. The effect of positive bias on annealing of radiation damage is obscured by the positive charge induced due to positive bias-temperature treatment alone. No effect of drain-to-source potential on annealing has been observed.     

Ge n-MOSFETs on lightly doped substrates with high-/spl kappa/ dielectric and TaN gate

In this letter, we report successful fabrication of germanium n-MOSFETs on lightly doped Ge substrates with a thin HfO/sub 2/ dielectric (equivalent oxide thickness /spl sim/10.8 /spl Aring/) and TaN gate electrode. The highest peak mobility (330 cm/sup 2//V/spl middot/s) and saturated drive current (130 /spl mu/A/sq at V/sub g/--V/sub t/=1.5 V) have been demonstrated for n-channel bulk Ge MOSFETs with an ultrathin dielectric. As compared to Si control devices, 2.5/spl times/ enhancement of peak mobility has been achieved. The poor performance of Ge n-MOSFET devices reported recently and its mechanism have been investigated. Impurity induced structural defects are believed to be responsible for the severe degradation.     

Hole and electron current transport inmetal-oxide-nitride-oxide-silicon memory structures

The carrier transport properties in metal-oxide (top oxide) nitride-oxide (tunnel oxide) silicon (MONOS) memory structures have been investigated in steady-state conditions under negative gate bias voltage. Carriers were separated into holes and electrons utilizing an induced junction of the p-channel MONOS transistors. Two-carrier transport is confirmed in the structure at negative gate polarity. It is found that the relatively thick top oxide acts as a potential barrier to the holes injected from the Si into the thin nitride. It is also found that a portion of the electrons injected from the gate at negative gate polarity recombine with the holes injected from the Si even in such a thin nitride and/or at the top-oxide/nitride interface     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Characteristics of a photonic crystal defect waveguide-coupled quantum-dot photodiode

We have investigated the characteristics of an In/sub 0.4/Ga/sub 0.6/As self-organized quantum-dot (QD) resonant-cavity photodiode. The QD epitaxy and the design of the two-dimensional photonic crystal cavity are tailored for 1.3-/spl mu/m wavelength operation. The input excitation to the photodiode is provided with an in-plane defect waveguide designed with the same photonic crystal. The measured spectral photocurrent characteristics reflect mode coupling between the waveguide and detector and the resonant cavity effect due to total internal reflection and photonic bandgap confinement. The photocurrent response is explained with a model involving the circulating fields in the cavity. The characteristics are also dependent of cavity size. Enhancement and narrowing (/spl sim/ 10 nm) of the photoresponse at /spl lambda//spl sim/1.3 /spl mu/m are observed. A spectral dip, of /spl sim/ 10-nm width, also observed at 1.3 /spl mu/m is possibly due to the anticrossing mechanism, uniquely present in photonic crystal waveguides.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

Room temperature continuous-wave operation of buried ridge stripe lasers using InAs-InP (100) quantum dots as active core

Self-organized InAs quantum-dot (QD) lasers emitting at 1.5 /spl mu/m were grown by gas source molecular beam epitaxy on (100) InP substrates. Room temperature continuous-wave (CW) operation of QD-based buried ridge stripe lasers is reported. We investigated experimentally the relevant CW performances of as-cleaved InP-based QD lasers for telecom applications such as temperature properties (T/sub 0/=56 K), infinite length threshold current density (J/sub /spl infin///spl sim/150 A/cm/sup 2/ per QDs layer) and internal efficiency (0.37 W/A). Lasing in pulsed mode is observed for cavity length as short as 200 /spl mu/m with a threshold current of about 37 mA, demonstrating the high gain of the QD's active core. In addition, the Henry parameter of these InP-based QD lasers is experimentally determined using the Hakki-Paoli method (/spl alpha//sub H//spl sim/2.2).     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAlP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-/spl mu/m gate lengths exhibit a cutoff frequency (f/sub t/) of 13.7 GHz and a maximum frequency of oscillation (f/sub max/) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8/spl times/10/sup -3/ A/cm/sup 2/ at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the /spl sim/ 11-nm thick native gate oxide.     

A physically based compact gate C-V model for ultrathin (EOT /spl sim/1 nm and below) gate dielectric MOS devices

A computationally efficient and accurate physically based gate capacitance model of MOS devices with advanced ultrathin equivalent oxide thickness (EOT) oxides (down to 0.5 nm explicitly considered here) is introduced for the current and near future integrated circuit technology nodes. In such a thin gate dielectric regime, the modeling of quantum-mechanical (QM) effects simply with the assumption of an infinite triangular quantum well at the Si-dielectric interface can result in unacceptable underestimates of calculated gate capacitance. With the aid of self-consistent numerical Schro/spl uml/dinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E/sub 1//spl prop/F/sub ox//sup 2/3/), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration. The filling of excited states consistent with Fermi statistics has been addressed. The quantum-corrected gate capacitance-voltage (C-V) calculations have then been tied directly to the Fermi level shift as per the definition of voltage (rather than, for example, obtained indirectly through calculation of quantum corrections to the charge centroids offset from the interface). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO/sub 2/, Si/sub 3/N/sub 4/ and high-/spl kappa/ (e.g., HfO/sub 2/) gate dielectrics on (100) Si with EOTs down to /spl sim/1.3 nm. The compact model has also been adapted to address interface states, and poly depletion and poly accumulation effects on gate capacitance.     

Ge outdiffusion effect on flicker noise in strained-Si nMOSFETs

The flicker noise characteristics of strained-Si nMOSFETs are significantly dependent on the gate oxide formation. At high temperature (900/spl deg/C) thermal oxidation, the Si interstitials at the Si/oxide interface were injected into the underneath Si-SiGe heterojunction, and enhanced the Ge outdiffusion into the Si/oxide interface. The Ge atoms at Si/oxide interface act as trap centers, and the strained-Si nMOSFET with thermal gate oxide yields a much larger flicker noise than the control Si device. The Ge outdiffusion is suppressed for the device with the low temperature (700/spl deg/C) tetraethylorthosilicate gate oxide. The capacitance-voltage measurements of the strained-Si devices with thermal oxide also show that the Si/oxide interface trap density increases and the Si-SiGe heterojunction is smeared out due to the Ge outdiffusion.     

Single-mode monolithic quantum-dot VCSEL in 1.3 /spl mu/m with sidemode suppression ratio over 30 dB

We present monolithic quantum-dot vertical-cavity surface-emitting lasers (QD VCSELs) operating in the 1.3-/spl mu/m optical communication wavelength. The QD VCSELs have adapted fully doped structure on GaAs substrate. The output power is /spl sim/330 /spl mu/W with slope efficiency of 0.18 W/A at room temperature. Single-mode operation was obtained with a sidemode suppression ratio of >30 dB. The modulation bandwidth and eye diagram in 2.5 Gb/s was also presented.     

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

Modeling study of the impact of surface roughness on silicon and Germanium UTB MOSFETs

We outlined a simple model to account for the surface roughness (SR)-induced enhanced threshold voltage (V/sub TH/) shifts that were recently observed in ultrathin-body MOSFETs fabricated on <100> Si surface. The phenomena of enhanced V/sub TH/ shifts can be modeled by accounting for the fluctuation of quantization energy in the ultrathin body (UTB) MOSFETs due to SR up to a second-order approximation. Our model is then used to examine the enhanced V/sub TH/ shift phenomena in other novel surface orientations for Si and Ge and its impact on gate workfunction design. We also performed a calculation of the SR-limited hole mobility (/spl mu//sub H,SR/) of p-MOSFETs with an ultrathin Si and Ge active layer thickness, T/sub Body/<10 nm. Calculation of the electronic band structures is done within the effective mass framework via the Luttinger Kohn Hamiltonian, and the mobility is calculated using an isotropic approximation for the relaxation time calculation, while retaining the full anisotropy of the valence subband structure. For both Si and Ge, the dependence of /spl mu//sub H,SR/ on the surface orientation, channel orientation, and T/sub Body/ are explored. It was found that a <110> surface yields the highest /spl mu//sub H,SR/. The increasing quantization mass m/sub z/ for <110> surface renders its /spl mu//sub H,SR/ less susceptible with the decrease of T/sub Body/. In contrast, <100> surface exhibits smallest /spl mu//sub H,SR/ due to its smallest m/sub z/. The SR parameters, i.e. autocorrelation length (L) and root-mean-square (/spl Delta//sub rms/) used in this paper is obtained from the available experimental result of Si<100> UTB MOSFETs, by adjusting these SR parameters to obtain a theoretical fit with experimental data on SR-limited mobility and V/sub TH/ shifts. This set of SR parameters is then employed for all orientations of both Si and Ge devices.