Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of “big-D/small-A” mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal “big-D/small-A” SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.      

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.     

Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores

For mixed-signal cores on System-on-a-Chip (SoC) platforms, the current methodology in test development is to use special test modes for block isolation such that mixed-signal cores are accessible from the chip boundary through a well-defined interface. Since the access mechanism to the core is preserved, this method facilitates fast test development when the core is re-used on another SoC. In order to obtain the shortest per-device test times on low-cost test platforms, we explore the option of operating the SoC in its designed functional mode where all on-chip resources are fully available for test support. We demonstrate this new method for a microcontroller with embedded ADCs. For high-volume products, the ultimate target is to minimize test costs by maximizing the efficiency of testing multiple devices in parallel on one tester. We demonstrate two benefits of testing in a functional mode that increases parallel test efficiency: (1) Simultaneous testing of multiple on-chip cores, and (2) On-chip post-processing to reduce the amount of test data.     

Switched-Current bandpass Sigma–Delta modulators for AM digital radio receivers

This paper discusses the use of switched-current (SI) circuits to design Band-Pass ΣΔ Modulators (BP-ΣΔMs) suitable for AM digital radio receivers. First of all, the paper briefly outlines the concept and principles of BP-ΣΔMs, and introduces two modulator architectures which are obtained by applying a lowpass-to-bandpass transformation (i.e. z⁻¹→−z⁻²) to a first-order and a second-order Low-Pass ΣΔ Modulator (LP-ΣΔM), respectively. The resulting BP-ΣΔMs, respectively of second-order and of fourth-order, are then used as case studies for SI circuit implementation. Systematic analysis of the errors associated to SI circuits is carried out and models are presented to evaluate their incidence on the performance of BP-ΣΔMs; the significance of the different errors is illustrated via the two selected case studies. Fully-differential regulated-folded cascode SI memory cells are chosen to attenuate these errors. Based on the proposed error models, optimization is carried out to fulfill AM radio requirements in practical modulator implementations. Two IC prototypes have been fabricated in a CMOS 0.8 μm technology, and measured, to validate the presented design methodology. One of these prototypes uses the fourth-order architecture to digitize AM signals, and features 10.5-bit resolution with 60 mW power consumption from a 5 V supply voltage. The other uses the second-order architecture and features 8-bit with 42 mW in the commercial AM band, from 540 to 1600 kHz. Experimental results show correct noise-shaping for sampling frequencies up to 16 MHz, which means a significant operation frequency enhancement as compared to previously reported SI ΣΔ Modulators.     

High temperature ohmic contacts to 3C–silicon carbide films

Currently, large-area 3C–SiC films are available from a number of sources and it is imperative that stable high temperature contacts be developed for high power devices on these films. By comparing the existing data in the literature, we demonstrate that the contact behavior on each of the different polytypes of SiC will vary significantly. In particular, we demonstrate this for 6H–SiC and 3C–SiC. The interface slope parameter, S, which is a measure of the Fermi-level pinning in each system varies between 0.4–0.5 on 6H–SiC, while it is 0.6 on 3C–SiC. This implies that the barrier heights of contacts to 3C–SiC will vary more significantly with the choice of metal than for 6H–SiC. Aluminum, nickel and tungsten were deposited on 3C–SiC films and their specific contact resistance measured using the circular TLM method. High temperature measurements (up to 400°C) were performed to determine the behavior of these contacts at operational temperatures. Aluminum was used primarily as a baseline for comparison since it melts at 660°C and cannot be used for very high temperature contacts. The specific contact resistance (ρ_c) for nickel at room temperature was 5×10⁻⁴ Ω cm², but increased with temperature to a value of 1.5×10⁻³ Ω cm² at 400°C. Tungsten had a higher room temperature ρ_c of 2×10⁻³ Ω cm², which remained relatively constant with increasing temperature up to 400°C. This is related to the fact that there is hardly any reaction between tungsten and silicon carbide even up to 900°C, whereas nickel almost completely reacts with SiC by that temperature. Contact resistance measurements were also performed on samples that were annealed at 500°C.     

Frequency dependence of of MOS capacitors

The frequency dependence of ΔV/Δ(C⁻²) of an MOS capacitor, which plays an important role in determining the semiconductor doping profile, is studied theoretically and experimentally. Useful expressions relating the measurable quantities to the doping profile are derived systematically. It is shown how interface states and majority carriers influence the frequency dependence of ΔV/Δ(C⁻²) and give rise to errors in profile determinations. The techniques of measuring the various types of the frequency dependence of ΔV/Δ(C⁻²) are also described.     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.     

Production Realization of MTPR Test on Low-Cost ATE for OFDM Based Communication Devices

Multi-tone power ratio (MTPR) test is fast replacing multiple single-carrier linearity and non-linearity tests for mixed-signal IC’s employed in broadband communication. Competitive cost models rule out the use of expensive automated test equipment that can perform MTPR test in a specification compliant manner. In this paper, deployment of a multi-tone dither based approach to perform MTPR tests on lower cost test platforms is presented. The proposed method uses existing resources of a low-cost ATE to improve the linearity performance of other resources required during the MTPR test. An ‘on-the-fly’ dither generation algorithm is developed to derive a robust dither signal accounting for variations typically encountered in production testing. Results obtained from multiple test benches including ADSL mixed-signal CODEC ICs on TI’s internal low-cost platform is presented to validate the proposed test method. Finally, statistical test data obtained from conducted experiments is presented to evaluate the repeatability of the proposed approach.     

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.     

On-Chip Evaluation of Oscillation-Based-Test Output Signals for Switched-Capacitor Circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approach.     

On Using Twisted-Ring Counters for Test Set Embedding in BIST

We present a novel built-in self-test (BIST) architecture for high-performance circuits. The proposed approach is especially suitable for embedding precomputed test sets for core-based systems since it does not require a structural model of the circuit, either for fault simulation or for test generation. It utilizes a twisted-ring counter (TRC) for test-per-clock BIST and is appropriate for high-performance designs because it does not add any mapping logic to critical functional paths. Test patterns are generated on-chip by carefully reseeding the TRC. We show that a small number of seeds is adequate for generating test sequences that embed complete test sets for the ISCAS benchmark circuits.Instead of being stored on-chip, the seed patterns can also be scanned in using a low-cost, slower tester. The seeds can be viewed as an encoded version of the test set that is stored in tester memory. This requires almost 10X less memory than compacted test sets obtained from ATPG programs. This allows us to effectively combine high-quality BIST with external testing using slow testers. As the cost of high-speed testers increases, methodologies that facilitate testing using slow testers become especially important. The proposed approach is a step in that direction.     

A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave Fitting

Sigma–Delta (ΣΔ) modulators have made possible the design of high-resolution Analogue-to-Digital Converters (ADCs) with relaxed analogue circuitry precision by moving most of the design complexity to the digital domain. However, testing these ΣΔ ADCs is becoming a costly task due to trends towards high-resolution implementations and associated increase in samples required to extract key specifications. In this paper, we propose a Built-In Self-Test (BIST) technique for high-resolution ΣΔ ADCs. The technique, mostly digital, moves most of the test complexity to the digital domain, that is in-line with the philosophy of ΣΔ modulation. Both the test signal generation and the output response analysis are performed on-chip. The stimulus, a sinusoid encoded in a binary bit stream, is chosen to have very high quality in the bandwidth of the converter with the quantization error laying outside of the analogue modulator’s bandwidth. For the output response analysis, a sine-wave fitting algorithm is implemented on chip. For this, a digital sinusoidal stimulus of a very high precision is needed as a reference signal. In this paper, we generate this reference signal from the same input stimulus, by passing it through the digital filter already existing in the converter. Simulations results show the capability of this technique to obtain measurements of the SNDR (Signal-to-Noise-plus-Distortion Ratio) for a 16-bit audio ΣΔ ADC.     

An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration

An on-chip multichannel waveform monitoring technique enhances built-in test and diagnostic capabilities of systems- on-a-chip (SoC) integration. The proposed multichannel monitor includes multiple probing front-end modules and a single shared waveform acquisition kernel that consists of an incremental variable step delay generator and an incremental reference voltage generator, featuring adaptive sample time generation for the operation of a target circuit and unidirectional waveform acquisition flow for area-efficient control. A 16-channel prototype in 0.18-mum CMOS technology demonstrated on-chip waveform acquisition at 40-ps and 200-muV resolutions. Combined on- and off-chip streamed-bit processing achieves background continuous waveform acquisition at 260 ms per single timing point for repetitive signals, while eliminating the integration of on-die high-capacity memory. A 700 mum times 600 mum area was occupied by a waveform acquisition kernel and an additional 60 mum times 100 mum area for each front-end module. The developed on-chip multichannel waveform monitoring technique is waveform accurate, area efficient, and suitable for diagnosis toward power supply and signal integrity in analog and digital circuits in mixed-signal SoC integration.     

Generating, capturing and processing supply current signatures from analogue macros in mixed-signal ASICs

Transient Response Testing is a powerful test technique for analogue macros in mixed-signal electronic systems which with some enhancement can be particularly useful for testing deeply buried circuit structures. Supply current testing is finding widespread application in the digital domain and its use in the analogue domain may lead to integrated test methodologies for mixed-signal systems. This paper shows that by utilizing both these techniques, and a low-cost test shell, deeply buried analogue macros can be partitioned, tested using Transient Response Testing and the resulting response accurately captured from the total device supply current. It also contains an analysis of the noise on the supply current, due to digital circuit activity during testing, and demonstrates a test response analysis technique which is insensitive to it.     

Analysis and application of digital spectral warping in analog and mixed-signal testing

Spectral warping is a digital signal processing transform which shifts the frequencies contained within a signal along the frequency axis. The Fourier transform coefficients of a warped signal correspond to frequency-domain 'samples' of the original signal which are unevenly spaced along the frequency axis. This property allows the technique to be efficiently used for DSP-based analog and mixed-signal testing. The analysis and application of spectral warping for test signal generation, response analysis, filter design, frequency response evaluation, etc. are discussed in this paper along with examples of the software and hardware implementation.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks.The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors.The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

Adaptive CMOS analog circuits for 4G mobile terminals—Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost.Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical.These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.     

Optimization of Al/a-SiC:H optical sensor device by means of thermal annealing

The optimization of optoelectronic properties of Al/a-SiC:H Schottky diodes grown as Al/a-SiC:H/c-Si(n) structures is studied by means of thermal annealing of a-SiC:H thin films. According to the spectral response of the Schottky diodes the measured quantum efficiency, η_measured, increases with increasing annealing temperature (400–600 °C), whereas η_measured decreases for T_a>600 °C. For T_a=600 °C, optimum material quality of a-SiC:H films is achieved and the spectral response of the Al/a-SiC:H/c-S(n) structures present very high and almost constant values (η_measured80%) for the whole range of wavelengths from 500 up to 850 nm. These results show that our Al/a-SiC:H/c-S(n) structures can be very attractive as optical sensors. Diffusion length calculations as well as the mobility by lifetime product (μτ)_p of the minority carriers (holes) of a-SiC:H films present a dependence on T_a similar to that of the measured quantum efficiency. Finally, the quantum efficiency of films processed with T_a=675 °C is found to increase when the Al/a-SiC:H/c-S(n) structures are exposed to hydrogen, a result that could be promising for the construction of a hydrogen detection sensor.