A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.      

A CMOS Backgate-Coupled QVCO Based on Back-to-Back Series Varactor Configuration for Minimal AM-to-PM Noise Conversion

A 3.3 GHz CMOS quadrature voltage-controlled oscillator (QVCO) with very low phase noise is presented. The back-to-back series varactor configuration is employed in the LC tank for minimizing the AM-to-PM noise conversion. The backgate coupling for quadrature phase inter-locking further eliminates the noise contribution from coupling transistors and also reduces power consumption. The implemented QVCO in 0.18 $mu{rm m}$ CMOS technology achieved very low phase noise of ${- 133}~{rm dBc}/{rm Hz}$ at 1 MHz offset, where the total power consumption is 4.4 mW from a 1.0 V supply. The chip has a very high FOM of ${- 196.6}~{rm dBc}/{rm Hz}$.      

A Low Phase-Noise QVCO With Integrated Back-Gate Coupling and Source Resistive Degeneration Technique

A 0.18 $mu$ m CMOS quadrature voltage-controlled oscillator with an extremely-low phase noise is presented. The excellent phase noise performance is accomplished by integration of the back-gate quadrature phase coupling and source resistive degeneration techniques into a complementary oscillator topology. The measured phase noise is as low as ${-}133$ dBc/Hz at 1 MHz offset from 3.01 GHz. The output phase imbalance is less than 1$^{circ}$ . The output power is $-1.25{pm} 0.5$ dBm and harmonic suppression is greater than 30.8 dBc. The oscillator core consumes 5.38 mA from a 1.5 V power supply. This QVCO achieves the highest figure-of-merit of ${-}193.5$ dBc/Hz.      

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain $(K_{VCO})$ variation was developed. For small $K_{VCO}$ variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 $mu{rm m}$ CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has $-$ 113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.      

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

A Low-Noise Wide-BW 3.6-GHz Digital $DeltaSigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital converter (TDC) with 6-ps raw resolution and first-order shaping of its quantization noise along with digital quantization noise cancellation to achieve integrated phase noise of less than 300 fs (1 kHz to 40 MHz). The synthesizer includes two 10-bit 50-MHz passive digital-to-analog converters for digital control of the oscillator and an asynchronous frequency divider that avoids divide-value delay variation at its output. Implemented in a 0.13-$mu$m CMOS process, the prototype occupies 0.95-mm$^{2}$ active area and dissipates 39 mW for the core parts with another 8 mW for the oscillator output buffer. Measured phase noise at 3.67 GHz carrier frequency is $-$108 and $-$150 dBc/Hz at 400 kHz and 20 MHz offset, respectively.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A Low Voltage Quadrature VCO Implemented With Series Frequency Doublers

Using the transformer coupling technique, this letter presents a new quadrature voltage-controlled oscillator (QVCO) with bottom series-coupled transistors. The proposed CMOS QVCO has been implemented with the TSMC $0.13~mu{rm m}$ 1P8M CMOS process, and the die area is $1.03 times 0.914~{rm mm}^{2}$. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz frequency offset is $-117.98~{rm dBc/Hz}$ at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is $-187.27~{rm dBc/Hz}$.      

On Parallelepiped-Shaped Passbands for Multidimensional Nonseparable ${bf M}$th-Band Low-Pass Filters

The “shape” of the desired frequency passband is an important consideration in the design of nonseparable multidimensional ($M$ -D) filters in $M$-D multirate systems. For $M$-D ${bf M}$th-band filters, the passband shape should be chosen such that the ${bf M}$th-band constraint is satisfied. The most commonly used shape of the passband for $M$-D ${bf M}$ th-band low-pass filters is the so-called symmetric parallelepiped (SPD) ${rm SPD}(pi {bf M}^{- {rm T}})$ . In this paper, we consider the more general parallelepiped passband ${rm SPD}(pi {bf L} ^{rm T})$, and derive conditions on $ {bf L} $ such that the ${bf M}$ th-band constraint is satisfied. This result gives some flexibility in designing $M$-D ${bf M}$th-band filters with parallelepiped shapes other than the commonly used case of $ {bf L} = {bf M}^{- 1}$. We present design examples of 2-D ${bf M}$th-band filters to illustrate this flexibility in the choice of $ {bf L} $.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the $f _{max}$ of the transistors. Using a standard 0.18 $muhbox{m}$ CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are $-hbox{15~dBm}$ and $-hbox{89~dBc}/hbox{Hz}$ , respectively. Operated at a 1.8 $~$V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.      

A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars

Design and implementation of a millimeter-wave dual-band frequency synthesizer, operating in the 24 GHz and 77 GHz bands, are presented. All circuits except the voltage controlled oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to simplify the reconfiguration of the division ratio inside the phase-locked loop. The 1 mm $, times , $0.8 mm synthesizer chip is fabricated in a 0.18 $mu{hbox{m}}$ silicon-germanium BiCMOS technology, featuring 0.15 $mu{hbox{m}}$ emitter-width heterojunction bipolar transistors. Measurements of the prototype demonstrate a locking range of 23.8–26.95 GHz/75.67–78.5 GHz in the 24/77 GHz modes, with a low power consumption of 50/75 mW from a 2.5 V supply. The closed-loop phase noise at 1 MHz offset from the carrier is less than ${- }$ 100$~$dBc/Hz in both bands. The frequency synthesizer is suitable for integration in direct-conversion transceivers for K/W-band automotive radars and heterodyne receivers for 94$~$GHz imaging applications.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

Low Phase Noise Differential Vackar VCO in 0.18 CMOS Technology

In this letter, we present the measured performance of a differential Vackar voltage-controlled oscillator (VCO) implemented for the first time in CMOS technology. The Vackar VCO provided good isolation between the LC tank and the loss-compensating active circuit; thus, excellent frequency stability was achieved over the frequency tuning range. The Vackar VCO was implemented using nMOS transistors and an LC tank in a 0.18 $mu{rm m}$ RF CMOS process. The oscillation frequency ranged from 4.85 to 4.93 GHz. The measured phase noise of the Vackar VCO at 1 MHz offset was $-124.9 ~{rm dB}/{rm Hz}$ at 4.9 GHz with a figure-of-merit (FOM) of $-188 ~{rm dBc}/{rm Hz}$.      

Low-Power Short-Range Radio CMOS Subharmonic RF Front-End Using CG-CS LNA

A 2.4-GHz fully integrated differential RF front-end was designed and implemented using 0.18-$mu{hbox {m}}$ CMOS process. This design was targeted for low-power and low-cost applications such as short-range radio in biomedical devices. This RF front-end consists of a common-gate common-source low-noise-amplifier, a frequency doubler passive subharmonic mixer, and a resistive source degeneration intermediate frequency buffer. It consumes 2.5 mA from a 1.8-V supply. It occupies 950$ mu{hbox {m}}times hbox{500} mu{hbox {m}}$ active area, which is only approximately 30% of that of the conventional RF front-end. This subharmonic RF front-end achieves 26-dB conversion gain, 9-dB noise figure and $-$10-dBm ${rm IIP}_{3}$.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

94 GHz Voltage Controlled Oscillator With 5.8% Tuning Range in Bulk CMOS

A 94 GHz fundamental mode voltage controlled oscillator (VCO) is demonstrated using low leakage transistors in a 65 nm digital CMOS process with six metal layers. It achieves a tuning range of 5.8% and phase noise of ${-}$ 106 dBc/Hz at 10 MHz offset from a 94.9 GHz carrier. The output power varies between ${-}$ 4 and ${-}$ 8 dBm over the tuning range. The VCO draws 6 mA bias current from a 1.5 V supply and 6 mA from a 0.8 V supply.