全数字延时锁定环及其应用

介绍了一种区别于锁相环(PLL)和基于压控延迟线(VCDL)的延时锁定环(DLL)、全部由纯数字电路实现的DLL电路.该电路用于消除时钟时延,全数字的结构使其无条件稳定,不会累积相位误差,而且具有良好的噪声敏感度、较低的功耗和抖动性能.使其在时延补偿和时钟调整的应用中具有优势,并可全部嵌入单个芯片中.文中分析了全数字DLL的工作原理及其结构,给出了其在现场可编程门阵列(FPGA)中的应用.     

Modeling the power and ground effects of BGA packages

Ground bounce noise and power supply noise are the major concerns in the electrical design of ball grid array (BGA) packages, therefore accurate models of the package's ground and power structures are needed for circuit simulators. This innovative new software is targeted for the engineer who, at his laptop PC, can rapidly generate accurate power and ground electrical models of an entire BGA package. Using the accepted approximation equations of Grover and Walker [1973 and 1990], the program was designed to be fast and portable contrasting other methods of modeling in which such attributes were sacrificed for greater accuracy. Operation consists of entering the available data, and in just minutes retrieving a parameter listing and two sub-circuit models simultaneously, one circuit for power and one for the ground of the package. The values of inductance and capacitance generated by the program closely match those generated by Grover, Walker, and Caggiano [1995, 1997]. The listing can be used as an evaluation tool for a specific package (e.g., during a design review when critical information is needed quickly) while the circuit models can be used in a simulation program with integrated circuit emphasis (SPICE) circuit simulation of the integrated circuit (IC). These separate models, designed with as few components as possible in order to reduce the complexity of the SPICE topology while still maintaining accuracy, can be either incorporated with signal package models or can be simulated alone     

A compact multilayer IC package model for efficient simulation, analysis, and design of high-performance VLSI circuits

A multilayered integrated circuit (IC) package structure is composed of many signal layers, power layers, and ground layers. Particularly, the whole planes are assigned for the power and ground of the system. Accordingly, the generic circuit representation of such a complicated multilayer IC package becomes too complicated to efficiently evaluate its electrical performance. In this work, a novel compact package circuit model for the efficient simulation and analysis of such complicated IC packages is presented. Unlike the conventional models, current distributions within the package are modeled by introducing a compact partial plane circuit model. Thus, the proposed package model is much simpler than the conventional generic circuit models, while its accuracy is preserved. Thereby, today's complicated IC packages can be efficiently evaluated and analyzed. Its accuracy and efficiency are verified by benchmarking it with a conventional generic package circuit model; this conventional model may not be practical to use for package evaluation and analysis. It is then shown that the proposed model can be efficiently applied for the signal integrity verification of complicated IC packages and high-performance VLSI circuits.     

On-Chip Power-Grid Simulation Using Latency Insertion Method

Ensuring the integrity of the power supply in the power distribution networks (PDNs) of a chip is essential for building reliable high-performance chips. To ensure the power integrity, accurate, and memory- and time-efficient simulation approaches for simulating the power-supply noise in the on-chip PDN are essential. In this paper, a finite-difference formulation based on the latency insertion method (LIM) has been employed for simulating the power-supply noise in the on-chip PDN. A new common-mode type equivalent circuit has been proposed. In this equivalent circuit, a capacitance to ideal ground may not be present at all the nodes. Further, the nodes can be capacitively coupled to each other. To avoid inverting a large nonbanded matrix, a small capacitance to ground is added to a node that did not have any capacitance to ground, and a small series inductance is added to any floating capacitor that did not have any series inductance. Approximate closed-form expressions to compute the values of these capacitances to ground and series inductances have been proposed. The accuracy of the LIM-enabled transient simulation and the accuracy of the proposed closed-form expressions have been demonstrated. The memory and time complexity of the simulation for each time step have been shown to be O(N_n) each, where N_n is the number of nodes in the equivalent circuit. Stability condition is derived for the first time for multidimensional inhomogeneous RLC circuit. A upper bound of the time step is derived from the stability condition. Using this bound on the time step, the runtime of the overall transient simulation has been estimated to be approximately proportional to N_n ^2-2.5 for N_n in the order of millions.     

Estimation of ground bounce effects on CMOS circuits

Ground bounce estimation is important to determine the impact of simultaneous switching of input/output (I/O) drivers and clock drivers on the performance of application-specific integrated circuits (ASIC's). In this paper, we develop models to estimate the peak and damped resonance noise of the ground and power bounce. These models are developed for both long and short channel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simple and suitable for hand calculation     

Fast low-power decoders for RAMs

Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an elegant analytical solution, though there have been no corresponding analytical results until now which include the resistive effects of the interconnect. Using simple RC models, we analyze the problem of optimally sizing the decoder chain with RC interconnect and find the optimum fan-out to be about 4, just as in the case of a simple buffer chain. As in the simple buffer chain, supporting a fan-out of 4 often requires noninteger number of stages in the chain. Nevertheless, this result is used to arrive at a tight lower bound on the delay of a decoder. Two simple heuristics for sizing of real decoder with integer stages are examined. We evaluate a simple technique to reduce power, namely, reducing the sizes of the inputs of the word drivers, while sizing each of the subchains for maximum speed, and find that it provides for an efficient mechanism to trade off speed and power. We then use the RC models to compare different circuit techniques in use today and find that decoders with two input gates for all stages after the predecoder and pulse mode circuit techniques with skewed N to P ratios have the best performance     

Propagation Delay of an RC-Chain With a Ramp Input

In this brief, two simple semi-analytical models which allow the estimation of the propagation delay of an RC-chain with a linear input are presented. The closed-form models can be used to evaluate the propagation delay of wires in modern VLSI and ULSI processes. The two approximations, a continuous function and a piecewise function, exhibit a maximum error lower than 15% at the end of the chain. The models have been validated extensively through circuit simulations. In particular, 1000 different RC-chains have been considered and simulated demonstrating the accuracy of the proposed models with respect to the most widely used Elmore delay metric     

Power minimization for dynamic PLAs

Dynamic programmable logic arrays (PLAs) which are built of the nor-nor structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the nor-nor structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the nand functionality on top of the nor structure, thus, lowering the switching activities in the product lines, as well as power consumption. Since there are many candidates for super product lines, we have developed a computer-aided design (CAD) algorithm based on the maximum weighted matching to find the optimal solution. We have performed experiments on a large set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. The post simulation results show significant reduction in power consumption. Among the experimental circuits, circuit alu3 has the highest power saving 62.9% with the delay overhead 5.4%, and circuit newpla2 has the lowest power saving with delay overhead 22.7%. In addition, circuit in4 improves the delay with 5.7%. On the average, the power consumption can be saved 55.8% and the delay overhead is merely 3.3% for 25 circuits.     

Time-domain approach for synthesising SPICE-compatible models of power delivery networks of printed circuit board

Resonance noise, or power/ground bounce noise, between the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to extract the equivalent circuit models of power/ground planes by time-domain reflection and time-domain transmission waveforms. The extracted model can accurately predict the resonance behaviour of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the HSPICE simulator for the consideration of power/ground bouncing noise in high-speed circuits.     

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations     

Analysis and optimization of BiCMOS gate circuits

A comprehensive view of an optimization strategy for BiCMOS gates is described. A simple gate delay model is proposed. BiCMOS gate delay, when optimized, is found to be expressed as A+B√F, where F is fanout and A and B are coefficients. Since the coefficients can be extracted by SPICE simulation, the delay prediction can be precise, while keeping the delay formula simple enough for circuit designers to derive useful expressions. A procedure for optimizing BiCMOS gates is studied. BiCMOS gate delay can be calculated quickly and optimized efficiently just by looking up a design table which is obtained from SPICE simulations. The procedure for making the design table is technology-independent. Once obtained, the design table can be applied to any design with the same device technology. A sizing strategy of cascaded BiCMOS buffers is derived from the simple delay model. In a 0.8 μm, 9 GHz, BiCMOS process, a BiCMOS-BiCMOS cascaded buffer is optimized when the scale-up factor between two consecutive stages is e ^2.3(≈10.0). A BiCMOS-CMOS cascaded buffer becomes the fastest when the scale-up factor, e^1.6(≈5.0), is employed. The optimization procedure and the sizing strategy can be used for several variants of the basic BiCMOS gate, because the delay model is based on basic circuit models for the variants     

Delay sensing for long-term variations and defects monitoring in safety–critical applications

The impact of parametric variations on digital circuit performance is increasing in nanometer Integrated Circuits (IC), namely of Process, power supply Voltage and Temperature (PVT) variations. Moreover, circuit aging also impacts circuit performance, especially due to Negative Bias Temperature Instability (NBTI) effect. A growing number of physical defects manifest themselves as delay faults (at production, or during product lifetime). On-chip, on-line delay monitoring, as a circuit failure prediction technique, can be an attractive solution to guarantee correct operation in safety–critical applications. Safe operation can be monitored, by predictive delay fault detection. A delay monitoring methodology and a novel delay sensor (to be selectively inserted in key locations in the design and to be activated according to user’s requirements) is proposed, and a 65 nm design is presented. The proposed sensor is programmable, allowing delay monitoring for a wide range of delay values, and has been optimized to exhibit low sensitivity to PVT and aging-induced variations. Two MOSFET models—BPTM and ST—have been used. As abnormal delays can be monitored, regardless of their origin, both parametric variations and physical defects impact on circuit performance can be identified. Simulation results show that the sensor is effective in identifying such abnormal delays, due to NBTI-induced aging and to resistive open defects.     

A Novel Time-Domain Approach for Extracting Broadband Models of Power Delivery NetworksWith Resonance Effect

Resonance noise, or power/ground bounce noise, on the power and ground planes of high-speed circuit packages is one of the main concerns of signal integrity or power integrity issues. A novel time-domain approach is proposed to synthesize the broadband models of the power/ground planes with resonance effect. Using waveforms either from measurements by time-domain reflectrometry or simulations by the finite-difference time-domain method, the time-domain step response of the planes is characterized with a pole-residue representation obtained through the matrix pencil method. Lumped circuit equivalent circuit models are then synthesized through the pole-residue representations. The synthesized model can accurately predict the resonance behavior of power/ground planes over a wide frequency range. These models can be efficiently incorporated into the currently available circuit simulator such as HSPICE for the consideration of power/ground bouncing noise in high-speed circuits. Three cases are tested to demonstrate the validity and broadband accuracy of the proposed approach.      

Double gate-MOSFET subthreshold circuit for ultralow power applications

In this paper, we propose MOSFETs that are suitable for subthreshold digital circuit operations. The MOSFET subthreshold circuit would use subthreshold leakage current as the operating current to achieve ultralow power consumption when speed is not of utmost importance. We derive the theoretical limit of delay and energy consumption in MOSFET subthreshold circuit, and show that devices that have an ideal subthreshold slope are optimal for subthreshold operations due to the smaller gate capacitance, as well as the higher current. The analysis suggests that a double gate (DG)-MOSFET is promising for subthreshold operations due to its near-ideal subthreshold slope. The results of our investigation into the optimal device characteristics for DG-MOSFET subthreshold operation show that devices with longer channel length (compared to minimum gate length) can be used for robust subthreshold operation without any loss of performance. In addition, it is shown that the source and drain structure of DG-MOSFET can be simplified for subthreshold operations since source and drain need not be raised to reduce the parasitic resistance.     

Ternary CAM Power and Delay Model: Extensions and Uses

Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search primitives on network processors and even custom application-specific integrated circuits (ASICs), achieving tight bounds on worst case performance with standard memories often requires a very careful analysis of all possible access patterns. An alternative, and often times more simple solution, is possible if a ternary CAM (TCAM) is used to perform a fully parallel search across the entire data set. Unfortunately, this parallelism means that large portions of the chip are switching during each cycle, causing large amounts of power to be consumed. While researchers at all levels of design (from algorithms to circuits) have begun to explore new ways of managing the power consumption, quantifying design alternatives is difficult due to a lack of available models. In this paper, we examine the structure of a modern TCAM and present a simple, yet accurate, power and delay model. We present techniques to estimate the dynamic power consumption and leakage power of a TCAM structure and validate the model using a combination of industrial TCAM datasheets and prior published works. Such a model is a critical first step in bridging the intellectual divide between circuit-level and algorithm-level optimizations. To demonstrate the utility of our model, we present an extensive analysis of the model by varying various architectural parameters and describe how our model can be easily extended to handle several circuit optimizations in the TCAM structure. In addition, we present a comparative study of SRAM and TCAM energy consumption to directly quantify the many design options which will be very useful for network designers to explore various power management schemes.     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

DC-DC电荷泵的研究与设计

以Dickson电荷泵的基本原理为出发点，研究了一种将正电压输入转为负电压输出的开关电容电路。由于开关电容的充放电特点，为确定电容时间常数，采用非交叠时钟控制信号避免了由于时钟交叠而造成的当电容充电还未完成即对下一级电容进行放电的现象。同时，参考功率MOS-FET的电容模型通过增大驱动电路的电流减小了开关管的上升延时，提高了开关动作的速度，使转换效率得到明显提高。此电路结构简单，性能优良，易于集成，可广泛应用于输出负电压的电源产品中。     

Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

In high performance integrated circuits phenomena like crosstalk, IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their effects are assuming increasing impact compromising circuits functionality and not only their performances.This paper suggests a methodology to evaluate and to prevent power supply noise generation in more and more increasing dimensions circuit blocks. The power supply busses modeling is addressed to find out actual parameters to face early in the design phase noise phenomena related to power distribution. In particular using the equations reported in this paper the designer has the possibility to control the global power bus noise generation depending on the design strategy used, on the library characteristics and on the given performance constraints.The appropriateness of the developed methodology seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a target noise reduction besides delay and power optimization.     

Accurate power supply and ground plane pair models [for MCMs]

In this paper, we derive a theory and method for the use of two-dimensional (2-D) discrete transmission lines (TL's) or discrete coupled transmission lines (CTL's) in modeling power supply and ground planes accurately. If the stray coupling between power or local ground and global ground is not significant, the discrete TL's model is used. Otherwise the discrete CTL's model is used. An arbitrarily shaped plane pair is discretized into a 2-D TL or CTL array by an automatic mesh algorithm. The equivalent distributed circuit, including skin loss effect at high frequencies, represents this power ground plane pair. The theory is extended to be applicable to a generic multiple dielectric layer structure. The model computation results are in excellent agreement with S parameter measurements for practical frequency ranges, including the first major resonant nulls and peaks. The null or peak of the S parameter frequency response represents the test port interaction with the resonant standing wave of these planes at that frequency. The resultant S parameter data of these models can be condensed into a simpler N port equivalent circuit to represent a larger hierarchical power and ground plane network for fast simulation