Semi-Iterative Analog Turbo Decoding

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 nm² in a 0.25-mum BiCMOS process.     

Improving Network-on-Chip-based Turbo Decoder Architectures

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth-reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support double-binary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40 % with a performance degradation of about 0.2 dB.     

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.     

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm² by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.     

Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%     

Memory-Efficient and High-Throughput Decoding of Quasi-Cyclic LDPC Codes

We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.     

Iterative turbo decoder analysis based on density evolution

We track the density of extrinsic information in iterative turbo decoders by actual density evolution, and also approximate it by symmetric Gaussian density functions. The approximate model is verified by experimental measurements. We view the evolution of these density functions through an iterative decoder as a nonlinear dynamical system with feedback. Iterative decoding of turbo codes and of serially concatenated codes is analyzed by examining whether a signal-to-noise ratio (SNR) for the extrinsic information keeps growing with iterations. We define a “noise figure” for the iterative decoder, such that the turbo decoder will converge to the correct codeword if the noise figure is bounded by a number below zero dB. By decomposing the code's noise figure into individual curves of output SNR versus input SNR corresponding to the individual constituent codes, we gain many new insights into the performance of the iterative decoder for different constituents. Many mysteries of turbo codes are explained based on this analysis. For example, we show why certain codes converge better with iterative decoding than more powerful codes which are only suitable for maximum likelihood decoding. The roles of systematic bits and of recursive convolutional codes as constituents of turbo codes are crystallized. The analysis is generalized to serial concatenations of mixtures of complementary outer and inner constituent codes. Design examples are given to optimize mixture codes to achieve low iterative decoding thresholds on the signal-to-noise ratio of the channel     

DVB-RCS Turbo码的研究及其实现

针对DVB-RCS中的双二进制Turbo码,提出一种新的改进译码方法.根据该改进算法,基于流水线设计思想,设计出硬件译码结构,给出时序图.结果表明,对于ATM和MPEG两种帧,其误比特性能比max-log-map算法提高0.2 dB.     

Efficient Computation of EXIT Functions for Nonbinary Iterative Decoding

The calculation of nonbinary extrinsic information transfer charts for the iterative decoding of concatenated index-based codes is addressed. We show that the extrinsic information at the output of a constituent a posteriori probability decoder can be calculated with very low complexity, where expensive histogram measurements are not required any more. An example for turbo trellis-coded modulation demonstrates the capabilities of the proposed approach     

Low-complexity iterative joint source-channel decoding for variable-length encoded Markov sources

In this paper, we present a novel packetized bit-level decoding algorithm for variable-length encoded Markov sources, which calculates reliability information for the decoded bits in the form of a posteriori probabilities (APPs). An interesting feature of the proposed approach is that symbol-based source statistics in the form of the transition probabilities of the Markov source are exploited as a priori information on a bit-level trellis. This method is especially well-suited for long input blocks, since in contrast to other symbol-based APP decoding approaches, the number of trellis states does not depend on the packet length. When additionally the variable-length encoded source data is protected by channel codes, an iterative source-channel decoding scheme can be obtained in the same way as for serially concatenated codes. Furthermore, based on an analysis of the iterative decoder via extrinsic information transfer charts, it can be shown that by using reversible variable-length codes with a free distance of two, in combination with rate-1 channel codes and residual source redundancy, a reliable transmission is possible even for highly corrupted channels. This justifies a new source-channel encoding technique where explicit redundancy for error protection is only added in the source encoder.     

Joint source-channel turbo coding for binary Markov sources

We investigate the construction of joint source-channel (JSC) turbo codes for the reliable communication of binary Markov sources over additive white Gaussian noise and Rayleigh fading channels. To exploit the source Markovian redundancy, the first constituent turbo decoder is designed according to a modified version of Berrou's original decoding algorithm that employs the Gaussian assumption for the extrinsic information. Due to interleaving, the second constituent decoder is unable to adopt the same decoding method; so its extrinsic information is appropriately adjusted via a weighted correction term. The turbo encoder is also optimized according to the Markovian source statistics and by allowing different or asymmetric constituent encoders. Simulation results demonstrate substantial gains over the original (unoptimized) Turbo codes, hence significantly reducing the performance gap to the Shannon limit. Finally, we show that our JSC coding system considerably outperforms tandem coding schemes for bit error rates smaller than 10/sup -4/, while enjoying a lower system complexity.     

Improving the Error Rate Performance of Turbo Codes using the Forced Symbol Method

This letter presents a method that significantly improves the error rate performance of turbo codes, especially in the error flare region, without changing the basic encoder structure. This method applies repeated decoding, with one or more symbols being forced to certain values, when an error is detected. This forces the decoder to output alternate sets of decisions that can then be checked for errors. The effectiveness of this method is demonstrated by its ability to lower the error flare by several orders of magnitude as soon as the error flare region is encountered. For the DVB-RCS 8-state, rate 1/2, double-binary turbo code and packets of 1504 information bits (MPEG-size), this method yields performance about 0.4 dB from the sphere-packing bound down to a packet error rate of 10-7.     

Convergence behavior of iteratively decoded parallel concatenatedcodes

Mutual information transfer characteristics of soft in/soft out decoders are proposed as a tool to better understand the convergence behavior of iterative decoding schemes. The exchange of extrinsic information is visualized as a decoding trajectory in the extrinsic information transfer chart (EXIT chart). This allows the prediction of turbo cliff position and bit error rate after an arbitrary number of iterations. The influence of code memory, code polynomials as well as different constituent codes on the convergence behavior is studied for parallel concatenated codes. A code search based on the EXIT chart technique has been performed yielding new recursive systematic convolutional constituent codes exhibiting turbo cliffs at lower signal-to-noise ratios than attainable by previously known constituent codes     

Joint turbo decoding and estimation of hidden Markov sources

We describe a joint source-channel scheme for modifying a turbo decoder in order to exploit the statistical characteristics of hidden Markov sources. The basic idea is to treat the trellis describing the hidden Markov source as another constituent decoder which exchanges information with the other constituent decoder blocks. The source block uses as extrinsic information the probability of the input bits that is provided by the constituent decoder blocks. On the other hand, it produces a new estimation of such a probability which will be used as extrinsic information by the constituent turbo decoders. The proposed joint source-channel decoding technique leads to significantly improved performance relative to systems in which source statistics are not exploited and avoids the need to perform any explicit source coding prior to transmission. Lack of a priori knowledge of the source parameters does not degrade the performance of the system, since these parameters can be jointly estimated with turbo decoding     

Bit-level soft-decision decoding of Reed-Solomon codes

A Reed-Solomon decoder that makes use of bit-level soft-decision information is presented. A Reed-Solomon generator matrix that possesses a certain inherent structure in GF(2) is derived. This structure allows the code to be represented as a union of cosets, each coset being an interleaver of several binary BCH codes. Such partition into cosets provides a clue for efficient bit-level soft-decision decoding. Two decoding algorithms are derived. In the development of the first algorithm a memoryless channel is assumed, making the value of this algorithm more conceptual than practical. The second algorithm, which is obtained as a modification of the first, does account for channel memory and thus accommodates a bursty channel. Both decoding algorithms are, in many cases, orders of magnitude more efficient than conventional techniques     

A Low Complexity Decoding Algorithm for Extended Turbo Product Codes

In this letter, we propose a low complexity algorithm for extended turbo product codes by considering both the encoding and decoding aspects. For the encoding part, a new encoding scheme is presented for which the operations of looking up and fetching error patterns are no longer necessary, and thus the lookup table can be omitted. For the decoder, a new algorithm is proposed to extract the extrinsic information and reduce the redundancy. This new algorithm can reduce decoding complexity greatly and enhance the performance of the decoder. Simulation results are presented to show the effectiveness of the proposed scheme.     

Distance based adaptive scaling in suboptimal iterative decoding

This article develops an alternative adaptive iterative Chase (1972) based decoding algorithm for block turbo/product codes. The decoder considers only a small subset of codewords, so that estimates of the extrinsic information are required in some cases. This article develops such an estimate based on code distance properties     

Memory-efficient path metric update method in map decoder implementation

A novel memory efficient path metric update is proposed for Maximum A Posteriori （MAP） decoder of turbo codes to reduce the memory requirement of state metric information calculation. For MAP decoder, the same memory can be shared by the forward and backward metrics with this metric update scheme. The forward and backward metrics update can be performed at the same time. And all of the extrinsic information can be calculated at the end of metric update. Therefore, the latency and area in the implementation will be reduced with the proposed metric update method.     

Turbo码的一种并行译码方案及相应的并行结构交织器研究

Turbo码基于MAP算法译码的递推计算所引入高的译码延迟限制了Turbo码在高速率数据传输中的应用。为了解决这个问题,该文提供了一种降低译码延迟的并行译码方法。并行处理方案的实现必须通过适当的交织以避免两个译码器对外信息读写的数据冲突。该文在分析了任意无冲突交织方式可能性的存在之后,给出了设计任意地适用于并行处理方案的S随机交织器的方法。仿真验证了并行译码方案的误比特性能。     

高存储效率的MAP译码器网格信息更新实现方法

本文提出一种新型的高存储效率的最大似然译码(MAP)译码器网格信息更新实现方法,该方法可以降低Turbo码译码器状态阵列计算对存储器的需求.利用该实现方法可以使得MAP译码器的前向网格信息和后向网格信息共享同一存储器,而且前向和后向的网格信息更新以及MAP译码产生的外部信息同时进行计算;因此该法可以提高Turbo译码的运算速度、降低存储器开销,进而降低Turbo译码电路实现时的硅片面积.