A Classical Parameter Identification Method and?a?Modern Test Generation Algorithm

Many methods have been presented for the testing and diagnosis of analog circuits. Each of these methods has its advantages and disadvantages. In this paper we propose a novel sensitivity analysis algorithm for the classical parameter identification method and a continuous fault model for the modern test generation algorithm, and we compare the characteristics of these methods. At present, parameter identification based on the component connection model (CCM) cannot ensure that the diagnostic equation is optimal. The sensitivity analysis algorithm proposed in this paper can choose the optimal set of trees to construct an optimal CCM diagnostic equation, and enhance the diagnostic precision. But nowadays increasing attention is being paid to test generation algorithms. Most test generation algorithms use a single value in the fault model. But the single values cannot substitute for the actual faults that may occur, because the possible faulty values vary over a continuous range. To solve this problem, this paper presents a continuous fault model for the test generation algorithm which has a continuous range of parameters. The test generation algorithm with this model can improve the treatment of the tolerance problem, including the tolerances of both normal and faulty parameters, and enhance the fault coverage rate. The two methods can be applied in different situations.     

时序电路测试生成新算法研究

为解决同步时序电路的测试难题,提高时序电路测试生成效率,进行了时序电路测试生成算法的研究,将粒子群优化算法应用在时序电路的测试生成中。为验证PSO算法性能,首先将其用于函数优化,能获得较好的优化结果。之后建立自动测试生成离散粒子群速度—位置模型,针对国际标准时序电路的验证结果表明,与同类算法相比,该算法可以获得较高的故障覆盖率和较小的测试矢量集。     

基于否定选择遗传算法的路径覆盖测试数据生成

路径覆盖是软件测试领域重要的测试方法之一.在搜索空间中,找到一组测试数据满足路径覆盖是一个具有挑战性的问题.因此,自动生成测试数据是软件测试的关键问题.文中提出一种基于否定选择遗传算法的路径覆盖测试数据生成方法,将否定选择策略融入遗传算法,动态优化遗传算法的种群数据,自动生成覆盖目标路径的测试数据.多个基准程序和工业程序的实验结果表明,与随机方法和遗传算法比较,文中方法能够提高路径覆盖率,减少冗余测试数据的生成.     

基于March X算法的SRAM BIST的设计

针对LS-DSP中嵌入的128kb SRAM模块,讨论了基于March X算法的BIST电路的设计.根据SRAM的故障模型和测试算法的故障覆盖率,讨论了测试算法的选择、数据背景的产生:完成了基于March X算法的BIST电路的设计.128kb SRAM BIST电路的规模约为2000门,仅占存储器面积的1.2%,故障覆盖率高于80%.     

基于蚂蚁算法和遗传算法的时序电路测试生成

为提高时序电路的测试生成效率,该文提出一种新的基于蚂蚁算法和遗传算法的时序电路测试矢量生成算法.针对国际标准时序电路的实验结果表明,该交叉算法既充分发挥了两种算法的优点,又克服了各自的缺点,与其它同类测试生成算法相比,获得了较好的故障覆盖率和测试集.说明采用蚂蚁算法和遗传算法的交叉算法是成功的.     

时序电路的模糊化测试生成算法

文章提出的模糊化的时序电路测试生成算法不明确指定故障点的故障值，它将故障值模糊化，并以符号表示。本算法第一阶段通过计算状态线和原始输出端的故障值来寻找测试矢量，通过计算故障点的正常值来 寻找测试矢量对应的故障类型；第二阶段用故障点的正常值作为约束条件计算故障点的另一个测试矢量。与传统的算法不同，它不需要回退和传播的过程。实验结果表明本算法具有较高的故障覆盖率和较少的测试时间。     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

一种片上网络路由测试方法研究

对片上网络路由器的结构进行了分析,建立了相应的故障模型.针对此故障模型结合内建自测试,提出了一种基于量子遗传算法的测试矢量传递路径寻优方法.该算法具有收敛速度快,精度高等优点.最后通过对测试故障覆盖率和测试时间进行分析表明这种测试方法具有较高的故障覆盖率、较少的测试时间.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

基于March C-算法的SRAM BIST电路的设计

针对某SOC中嵌入的8K SRAM模块,讨论了基于March C-算法的BIST电路的设计.根据SRAM的故障模型和测试算法的故障覆盖率,研究了测试算法的选择、数据背景的产生,并完成了基于March C-算法的BIST电路的设计.实验证明,该算法的BIST实现能大幅提高故障覆盖率.     

测试不可靠条件下基于量子进化算法的测试优化选择

测试优化选择是复杂电子系统测试性设计中的一个重要问题.首先从测试容差的角度分析了测试发生漏检和虚警的原因,在此基础上建立了测试不可靠条件下一种新的测试选择模型,模型以测试代价、漏检代价和虚警代价之和最小为优化目标,以故障检测率和故障隔离率为约束条件;然后提出一种改进的量子进化算法对模型求解,该算法通过改进一种已有可靠测试选择算法而成,包括种群初始化、适应度计算和种群的进化策略.最后通过两个仿真实例验证了求解算法及模型的有效性和优越性.     

人工鱼群优化的方向传感器覆盖增强

为提高无线多媒体传感器网络区域覆盖率,提出了人工鱼群优化的覆盖增强算法,算法基于三维方向传感器感知模型,优化网络传感器方向角度值,减少重叠覆盖以提升网络覆盖率。仿真实验表明该方法能有效增强网络覆盖率,并就传感器参数对覆盖率影响进行分析,分析结果表明优化后的网络覆盖率更加接近理想覆盖率。     

Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation

This paper presents a new algorithm for the generation of test sequences for finite state machines. Test sequence generation is based on the transition fault model, and the generation of state-pair distinguishing sequences. We show that the use of state-pair distinguishing sequences generated from a fault-free finite state machine will remain a distinguishing sequence even in the presence of a single transition fault, thus guaranteeing complete single transition fault coverage. Analysis and experimental results show that the complexity of the test sequence generation algorithm is less than those of the previous algorithms. The utility of the transition fault model, and the generated test sequences is shown by their application to sequential logic circuits. These results show more than a factor of 10 improvement in the test generation time and some reduction in test length while maintaining 100% transition fault coverage.Now with Intel Corporation, FM5-161, 1900 Prairie City Road, Folsom, CA 95630.Now with Chrysalis Symbolic Design, 101 Billerica Ave., North Billerica, MA 01862.     

基于蚁群算法的多路径覆盖测试数据生成

为了提高多路径覆盖测试数据的生成效率,研究了一种基于蚁群算法的多路径覆盖测试数据生成方法.首先给出蚁群算法的一种改进方法,该算法以蚂蚁对生成测试数据的重要性作为蚂蚁状态转移和蚂蚁路径变异的依据,以引导更多蚂蚁穿越小概率节点,提高测试数据生成效率.其次,根据改进的蚁群算法分别提出了基于单信息素表和多信息素表的多路径覆盖测试数据生成方法.在基于多信息素表的方法中,每条目标路径的信息素表均被用于其它路径测试数据的求解,而且蚁群算法运行一次即可求解多条目标路径的覆盖测试数据.最后对所提出方法的有效性和复杂度进行了理论分析.实验结果表明,与其它方法相比,基于多信息素表的测试数据生成方法能够有效地生成多路径覆盖测试数据.     

电路测试神经网络方法中求多个测试矢量

文章研究在数字电路测试的神经网络方法中求给定故障对应的多个测试矢量的方法,首先提出了一种求多个测试矢量的遗传进化方法,然后提出了一种矢量扰动方法,通过这两种者的结合使用,能获得被测电路较小的完备测订,从而提高了电路测试神经网络的方法的性能。     

A technique to generate feasible tests for communications systems with multiple timers

We present a new model for testing real-time protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timer-related variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of feasible test sequences without compromising their fault coverage. The model is specifically designed for testing to avoid performing full reachability analysis, and to control the growth of the number of test scenarios. Based on extended finite state machines, it is applicable to languages such as SDL, VHDL, and Estelle. The technique models a realistic testing framework in which each I/O exchange takes a certain time to realize and timers can be arbitrarily started or stopped. A software tool implementing this technique is used to generate test cases for the US Army wireless standard MIL-STD 188-220.     

低电压SRAM测试电路设计与实现

本文基于SMIC 40nm LL CMOS工艺对一款256Kb的低电压8T SRAM芯片进行测试电路设计与实现,重点研究低电压SRAM的故障模型和测试算法,并完成仿真验证与分析。电路主要包括DFT电路和内建自测试电路两部分,前者针对稳定性故障有着良好的覆盖率,后者在传统March C+算法基础上,提出了一种新的测试算法,March-Like算法,该算法能够实现更高的故障覆盖率。仿真结果表明,本文设计的DFT电路能够减小稳定性故障的最小可检测电阻,提高了稳定性故障的测试灵敏度;March-Like算法可以检测到低电压SRAM阵列中的写破坏耦合故障、读破坏耦合故障和写干扰故障。     

Bayes analysis for fault location in distributed systems

The authors propose a simple and practical probabilistic model, using multiple incomplete test concepts, for fault location in distributed systems using a Bayes analysis procedure. Since it is easier to compare test results among processing units, their model is comparison-based. This approach is realistic and complete in the sense that it does not assume conditions such as permanently faulty units, complete tests, and perfect or nonmalicious environments. It can handle, without any overhead, fault-free systems so that the test procedure can be used to monitor a functioning system. Given a system S with a specific test graph, the corresponding conditional distribution between the comparison test results (syndrome) and the fault patterns of S can be generated. To avoid the complex global Bayes estimation process, the authors develop a simple bitwise Bayes algorithm for fault location of S, which locates system failures with linear complexity, making it suitable for hard real-time systems. Hence, their approach is appealing both from the practical and theoretical points of view     

基于遗传算法的Fuzzing测试用例生成模型

将遗传算法运用到Fuzzing的数据生成过程中,根据具体的测试目标特点,对遗传算法的各个部分进行了定义,适应度函数的设计引入了代码覆盖率和多样性因素.对模型进行初步实现,实验证明了该模型在Fuzzing过程中引导测试方向的有效性.     

基于测试向量中不确定位的漏电流优化技术

众所周知,CMOS电路测试时由漏电流引起的漏电流功耗在测试功耗中处于重要地位.降低测试时的漏电流对于延长需要周期性自测试的便携式系统电池寿命、提高测试的可靠性和降低测试成本都至关重要.文章首先分析了漏电流的组成,和与之相关的晶体管的堆栈效应.然后,我们提出了一种基于测试向量中不确定位(X位)、使用遗传算法优化集成电路测试时漏电流的方法.实验结果证明在组合电路和时序电路测试中该方法能够在不影响故障覆盖率的条件下,有效优化测试时电路的漏电流.