Reliability Investigation of 0.18-μm SOI MOS Transistors at High Temperatures

In this paper, we estimate the basic parameters of 0.18-μm SOI MOS transistors in the temperature range from –60 to 300°С and investigate their reliability at high temperatures. The specific characteristics of SOI MOS transistors that manifest themselves at high temperatures should be taken into account when designing high-temperature integrated circuits in order to avoid their premature failures and improve the reliability of electronic devices.     

Peculiarities of three-dimensional simulation of SOI MOS transistors with an indirect gate

A methodology for a three-dimensional (3D) simulation of submicron SOI MOS transistors, taking into account a lithographic topology distortion, is presented. The peculiarities of constructing a 3D structure are considered. An efficient method for grid generation is proposed. The results of simulating O-type SOI MOS transistors with and without precorrection of topology are given.     

Bipolar mechanisms present in short channel SOI-MOSFET transistors

The set of physical mechanisms present in the body of SOI MOS transistors has been presented. Selected bipolar aspects of physical phenomena usually oversimplified in existing SOI MOS models have been analyzed. The action of parasitic bipolar transistor present in the body of SOI MOS transistor is one of them and seems to become especially important as transistor channel dimensions are reduced.     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes

Demonstration of high-performance MOS thin-film transistors (TFTs) on elastically strain-sharing single-crystal Si/SiGe/Si nanomembranes (SiNMs) that are transferred to foreign substrates is reported. The transferable SiNMs are realized by first growing pseudomorphic SiGe and Si layers on silicon-on-insulator (SOI) substrates, and then, selectively removing the buried oxide (BOX) layer from the SOI. Before the release, only the SiGe layer is compressively strained. Upon release, part of the compressive strain in the SiGe layer is transferred to the thin Si layers, and the Si layers, thus, become tensile strained. Both the initial compressive strain state in the SiGe layer and the final strain sharing state between the SiGe and the Si layers are verified with X-ray diffraction measurements. The TFTs are fabricated employing the conventional high-temperature MOS process on the strain-shared SiNMs that are transferred to an oxidized Si substrate. The transferred strained-sharing SiNMs show outstanding thermal stability and can withstand the high-temperature TFT process on the new host substrate. The strained-channel TFTs fabricated on the new host substrate show high current drive capability and an average electron effective mobility of 270 cm²/V ldr s. The results suggest that transferable and thermally stable single-crystal elastically strain- sharing SiNMs can serve as excellent active material for high-speed device application with a simple and scalable transfer method. The demonstration of MOS TFTs on the transferable nanomembranes may create the opportunity for future high-speed Si CMOS heterogeneous integration on any substrate.     

Increased drain saturation current in ultra-thinsilicon-on-insulator (SOI) MOS transistors

Based on substrate-charge considerations, an increased drain saturation current for MOS transistors in ultrathin silicon-on-insulator (SOI) films is predicted, compared to similar transistors in bulk or thick SOI films. For typical parameters of 200-A gate oxide with a channel doping of 4×10¹⁶ cm^-3, the drain saturation current in ultrathin SOI transistors is predicted to be ~40% larger than that of bulk structures. An increase of ~30% is seen in measurements made on devices in 1000-A SOI films     

Demonstration of the potential of accumulation-mode MOS transistorson SOI substrates for high-temperature operation (150-300°C)

Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300°C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data     

Stacked CMOS circuits integrated in laser-recrystallized silicon films

Laser-recrystallized poly-silicon films are used as a substrate for the integration of MOS transistors and CMOS circuits. Ring oscillators and frequency divider circuits up to 100 transistors operate well with a yield of about 80%. For the integration of stacked CMOS circuits already tested bulk structures are covered with a dielectric layer and a poly-silicon film which is recrystallized at low temperature. The SOI integration technique, with a maximum temperature treatment of 960°C, is employed to manufacture the second active area as a 3-D technology. After the integration process SOI and bulk CMOS transistors operate independently at two different active levels.     

A low-frequency noise study of gate-all-around SOI transistors

The low-frequency noise characteristics of both n- and p-type gate-all-around (GAA) SOI MOS transistors are reported and compared with the noise behavior of conventional, partially depleted (PD) SOI transistors. It is shown that the input-referred noise of n-channel GAA transistors is considerably lower than for standard ones, which is related to the higher device transconductance, coupled to the occurrence of volume inversion, P-channel devices have a one order of magnitude lower noise spectral density than n-MOSTs, which is due to the corresponding lower density of interface traps. GAA p-MOSTs tend to have a lower average noise in weak inversion than their standard-SOI counterparts. In strong inversion, the reverse situation is often found. Finally, it is shown that in n-type GAA transistors no kink-related excess noise is observed, which is an additional benefit for using this type of SOI technology     

Reliability issues of scaled-down MOS transistors for gigabit circuits

The basic reliability issues of very small MOS transistors are addressed in this review and reliability constraints, such as trap-assisted tunneling, current increase at corner regions, oxide stability, oxide damage during processing, and hot carrier degradation are discussed. No major problems are expected for MOS transistors scaled down to their physical limits.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

High-temperature off-state characteristics of thin-SOI powerdevices

High-temperature off-state characteristics of thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically and compared with off-state characteristics of junction-isolated bulk-Si power devices. At 200°C, the off-state leakage current in the SOI devices was approximately 200 times lower than in the bulk-Si devices with a comparable breakdown voltage and on-resistance. At 300°C, well beyond the operating range of the bulk devices, the off-state leakage current in the SOI devices was only 1.5 nA/μm. The leakage current appears to scale with the thickness of the SOI layer. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications     

Behavior of analog MOS integrated circuits at high temperatures

Thermal effects on small-signal characteristics of MOS transistors are studied and parameters of MOS amplifiers operating at high temperatures are calculated. The predicted performance has been experimentally verified and high-temperature measurements of an operational amplifier and a switched-capacitor precision amplifier are presented.     

Study of thermal effects and self-heating phenomena in planar power SOI MOS transistors

Heat removal problems, thermal effects, and self-heating phenomena occurring during operation of planar power SOI MOS transistors are considered. Using device-technological simulating methods, the transistor characteristics and safe operation range were studied. It was shown that limitations of the safe operation range are mostly associated with structure self-heating rather than with the parasitic bipolar transistor.     

Efficiency of SOI-like structures for reducing the thermal resistance in thin-film SOI power LDMOSFETs

Silicon-on-insulator (SOI)-like structures to remove the heat from the active silicon layer in thin-film SOI power lateral double diffused MOS field-effect transistors have been recently reported. This paper provides an experimental demonstration of their efficiency. For this purpose, a heater-sensor system based on poly-Si and platinum resistor stripes, respectively, has been integrated in thermal contact with the active silicon layer under study. The thermal resistance reduction due to the contact-through-buried-oxide technique and the SOI-multilayer substrates have been analyzed at steady state using different SOI layer thicknesses and heat source lengths, in accordance with the state-of-the-art. In addition, experimental results are supported by those extracted from numerical simulation of the heater-sensor system.     

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.     

铁氧体驱动与双路功率MOS单片集成电路研究

介绍了一种集成低压铁氧体驱动器和功率MOS管的单片集成电路。其内建驱动器工作电压9 V,功率MOS管极限电压大于80 V,工作电流3 A。该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。     

Numerical study of self-heating effects of MOSFETs fabricated on SOAN substrate

A two-dimensional numerical analysis is performed to investigate the self-heating effects of metal-oxide-silicon field-effect transistors (MOSFETs) fabricated in silicon-on-aluminum nitride (SOAN) substrate. The electrical characteristics and temperature distribution are simulated and compared to those of bulk and standard silicon-on-insulator (SOI) MOSFETs. The SOAN devices are shown to have good leakage and subthreshold characteristics. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOAN can mitigate the self-heating penalty effectively. Our study suggests that AlN is a suitable alternative to silicon dioxide as the buried dielectric in SOI, and expands the applications of SOI to high temperature.     

全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100 V and average leakage current densities at 70 V were only 55 nA/cm². MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45 × 10¹¹ cm^?2 for a dose of 2.7 Mrad.