面向圆片级气密封装的表面活化直接键合技术

通过封装实验和性能检测,成功验证了表面活化直接键合技术应用于圆片级气密封装的可行性.实验中使用刻蚀出方形槽的硅圆片,通过化学表面活化方法.与基板硅圆片在室温下成功预键合,形成气密腔体;经过350℃、5 h的大气环境退火后强化了键合强度及气密性能.利用红外透射方法检测了键合后的硅圆片,其界面完整无明显空洞;键合界面横截面SEM图像显示键合界面均匀平整无显著缺陷.键合而成的气密腔体依次经过氦质谱仪和氟油检漏仪检测其气密性,平均漏率达到了1.175×10-8Pa·m3/s.     

谐振式MEMS压力传感器的制作及圆片级真空封装

为了提高传感器的品质因数,有效保护谐振器,提出了一种基于绝缘体上硅(SOI)-玻璃阳极键合工艺的谐振式微电子机械系统(MEMS)压力传感器的制作及真空封装方法。该方法采用反应离子深刻蚀技术(DRIE),分别在SOI晶圆的低电阻率器件层和基底层上制作H型谐振梁与压力敏感膜;然后,通过氢氟酸缓冲液腐蚀SOI晶圆的二氧化硅层释放可动结构。最后,利用精密机械加工技术在Pyrex玻璃圆片上制作空腔和电连接通孔,通过硅-玻璃阳极键合实现谐振梁的圆片级真空封装和电连接,成功地将谐振器封装在真空参考腔中。对传感器的性能测试表明:该真空封装方案简单有效,封装气密性良好;传感器在10kPa~110kPa的差分检测灵敏度约为10.66 Hz/hPa,线性相关系数为0.99999 542。     

MEMS器件的W2W真空封装研究

开发了一种适于MEMS器件的基于W2W(圆片对圆片)工艺的简易的圆片级真空封装方法。通过电镀工艺在MEMS器件圆片和封盖圆片上各沉积含5μm Cu和1.5μm Sn金属层的键合环。器件圆片和封盖圆片在160℃及0.01Pa的真空环境中保持10 min以形成真空,之后在270℃及4 MPa保持30 min通过Cu和Sn的互溶扩散工艺完成键合。测量键合区内Cu元素和Sn元素的重量比,证实形成了Cu3Sn和Cu6Sn5金属间化合物。通过剪切力测试对单个芯片的键合面强度进行标定,计算剪切强度达32.20 MPa。     

多功能真空键合设备的研制

基于圆片键合技术，设计了一种在真空条件下进行圆片键合的工艺设备。在该设备的基础上，进行了阳极键合与金硅键合2种典型的键合试验，键合出来的样品结合强度高而且没有缺陷，验证了该设备的实用性。     

芯片级原子器件MEMS碱金属蒸气腔室制作

提出了基于两步低温阳极键合工艺的碱金属蒸气腔室制作方法,用于实现原子钟、原子磁力计及原子陀螺仪等器件的芯片级集成.由微机电系统(MEMS)体硅工艺制备了腔室结构.首先采用标准工艺将刻蚀有腔室的硅圆片与Pyrex玻璃阳极键合成预成型腔室,然后引入氮缓冲气体和由惰性石蜡包覆的微量碱金属铷或铯.通过两步阳极键合来密封腔室,键合温度低于石蜡燃点198℃.第一步键合预封装腔室,键合电压小于缓冲气体的击穿电压.第二步键合在大气氛围中进行,电压增至1 200 V来增强封装质量.通过高功率激光器局部加热释放碱金属,同时在腔壁上形成均匀的石蜡镀层以延长极化原子寿命.本文实现了160℃的低温阳极键合封装,键合率达到95％以上.封装的碱金属铷释放后仍具有金属光泽,实现的最小双腔室体积为6.5 mm×4.5 mm×2 mm.铷的吸收光谱表明铷有效地封装在腔室中,证明两步低温阳极键合工艺制作碱金属蒸气腔室是可行的.     

基于MEMS器件的玻璃通孔内金属批量化填充制备

基于TGV(玻璃通孔)工艺实现圆片级真空封装的导线互联过程中,进行批量化的玻璃通孔金属填充是产品制备的必然选择。调研了玻璃加工的刻蚀技术,确定使用喷砂工艺制备通孔,基于孔径和形貌设计了两种电镀方案均实现了金属对孔的密封,通过比较2次电镀的时间和形貌,最终确定了双面溅射种子层进行电镀的方案,实现了批量化的TGV工艺制备。     

MEMS封装中阳极键合技术的影响因素研究和设计因素分析

结合MEMS气密性封装的需要,以玻璃与硅晶片阳极键合为例,给出阳极键合的封装工艺,从键合机理的角度研究了玻璃与硅阳极键合的影响因素,并就玻璃与硅阳极键合的设计因素做了分析,得到直径为100mm的Pyrex7740玻璃晶片和硅晶片在键合温度为500℃时,硅晶片的径向应力σrr=134.29MPa;键合后晶片的径向膨胀μ=0.1274mm。     

基于硅硅键合技术的高精度压力传感器的研究

硅压阻压力传感器核心部件一般是由单晶硅和玻璃组成的微结构,由于单晶硅和玻璃的材料特性存在差异,在制造过程中会引入封装应力对传感器的性能产生不利影响。采用硅硅键合技术制造压力传感器核心部件的微结构,以同质材料替代异质材料实现器件的封装,可有效减少封装应力,提升压力传感器的性能。文中通过结合硅压阻压力敏感芯片的制造工艺和硅硅键合工艺,实现了敏感芯片与硅衬底间的硅硅键合,键合强度达到体硅强度。研制的差压型压力敏感芯片装配成传感器的零点温度漂移下降60%,静压误差下降约1个数量级。     

谐振式MEMS压力传感器的设计与分析

提出一种基于静电激励/压阻检测的硅微谐振式压力传感器,该器件采取面内动平衡的振动模式,为了抑制压力敏感膜片受压变形时谐振器的高度变化,在谐振器固定端设计了悬置扭转结构。根据对传感器数学模型的分析与建立,并利用MEMS有限元仿真软件对传感器在0～120 kPa范围以及全范围过压1.5倍下进行模拟分析与仿真验证,初始频率为24.01 kHz,传感器灵敏度达18 Hz/kPa。利用硅-硅键合技术实现压力传感器的真空封装,并通过TSV通孔技术将传感器与电路芯片进行三维混合集成封装。     

基于皮拉尼的数字式称重传感器诊断技术

湿润空气会对称重传感器内部的元器件产生影响,降低产品的可靠性。本文阐述了一种将皮拉尼真空原理应用于数字式称重传感器中,以检测其内置的元件是否暴露于湿润空气中的方法。     

射频微系统2. 5D/3D 封装技术发展与应用

2. 5D/3D 封装技术是满足未来射频系统更高集成度、更高性能、更高工作频率需求的主要手段。文中介绍了目前微系统2. 5D/3D 封装技术的发展趋势及硅通孔(TSV)、微凸点/ 铜柱、圆片级封装等先进的高密度封装技术,并关注了2. 5D/3D 封装技术在射频微系统领域的应用及挑战,为射频微系统集成封装技术研究提供参考。     

The electrostatic-alloy bonding technique used in MEMS

Electrostatic-alloy bonding of silicon wafer with glass deposited by Au to form Si/Au-glass water, and bonding of Si/Au-glass with silicon wafer were researched during fabrication of pressure sensors. The silicon wafer and glass wafer with an Au film resistor were bonded by electrostatic bonding, and then Si-Au alloy bonding was formed by annealing at 400°C for 2 h. The air sealability of the cavity after bonding was finally tested using the N₂ filling method. The results indicate that large bond strength was obtained at the bonding interface. This process was used in fabricating a pressure sensor with a sandwich structure. The results indicate that the sensor presented better performances and that the bonding techniques can be used in MEMS packaging. __________ Translated from Journal of Harbin Institute of Technology, 2005, 37(1) (in Chinese)     

硅微陀螺仪器件级真空封装技术研究

为进一步提高硅微陀螺仪的品质因数及其稳定性,研究了硅微陀螺仪器件级真空封装的高真空获取技术和真空保持技术。首先,以硅微陀螺仪动力学方程为基础,分析了硅微陀螺仪的误差信号与品质因数之间的关系,并采用稀薄气体动力学分析具有高品质因数陀螺仪的空气阻尼。根据早期真空封装陀螺仪的品质因数跟踪测试曲线,分析了品质因数下降原因。采用程序升温脱附职谱分析法（TPD-MS）分析陶瓷管壳和金属盖板的放气特性,并选用了合理的吸气剂。最后,改进了器件级真空封装流程。测试结果表明,采用改进的器件级真空封装的陀螺仪品质因数最高可达162660,约为早期真空封装陀螺仪品质因数的14倍,且在一年内的变化小于0.05%。     

Analysis on annealing-induced stress of blind-via TSV using FEM

Copper-filled through silicon via (TSV) is a promising material owing to its application in high-density three-dimensional (3D) packaging. However, in TSV manufacturing, thermo-mechanical stress is induced during the annealing process, often causing reliability issues. In this paper, the finite element method is employed to investigate the impacts of via shape and SiO₂ liner uniformity on the thermo-mechanical properties of copper- filled blind-via TSV after annealing. Top interface stress analysis on the TSV structure shows that the curvature of via openings releases stress concentration that leads to ~60 MPa decrease of normal stresses, σ_xx and σ_yy, in copper and ~70 MPa decrease of σ_xx in silicon. Meanwhile, the vertical interface analysis shows that annealing-induced stress at the SiO₂/Si interface depends heavily on SiO₂ uniformity. By increasing the thickness of SiO₂ linear, the stress at the vertical interface can be significantly reduced. Thus, process optimization to reduce the annealing-induced stress becomes feasible. The results of this study help us gain a better understanding of the thermo-mechanical behavior of the annealed TSV in 3D packaging.     

基于Ka波段分布式MEMS移相器芯片微封装研究

本文提出一种适用于Ka波段分布式MEMS移相器的新型封装结构——具有垂直互连线的薄硅作为分布式MEMS移相器衬底，并用芯片微封装方法对移相器进行封装。采用CST模拟软件研究封装结构对移相器射频性能影响，模拟结构表明：当封装结构衬底厚度、垂直互连线半径和空腔高度分别为450μm、50μm和80μm时，Ka波段分布式MEMS移相器的插入损耗小于0．55dB，回波损耗优于12dB，相移量具有很好的线性关系，说明该新型封装结构非常适合RFMEMS器件低成本批量封装。     

Improvement of EDM efficiency of silicon single crystal through ohmic contact

This paper describes the improvement of the machining rate of electrical discharge machining (EDM) for silicon single crystals by reducing the contact resistance between the silicon single crystal and metal electric feeder. To decrease the resistance of the rectifying contact between a p-type silicon wafer and the metal feeder, attempts to achieve ohmic contact were made by plating the contact surface of the silicon wafer with aluminum by vacuum evaporation, followed by the diffusion process. To accomplish an ohmic contact between n-type silicon and metal, gold–antimony alloy was used in place of aluminum. The influence of polarity on the machining rate is also discussed from the viewpoint of the rectifying nature of the interface between the arc plasma and silicon single crystal.     

Loss budget of a setup for measuring mechanical dissipations of silicon wafers between 300 and 4 K

A setup for measuring mechanical losses of silicon wafers has been fully characterized from room temperature to 4 K in the frequency range between 300 Hz and 4 kHz: it consists of silicon wafers with nodal suspension and capacitive and optical vibration sensors. Major contributions to mechanical losses are investigated and compared with experimental data scanning the full temperature range; in particular, losses due to the thermoelastic effect and to the wafer clamp are modeled via finite element method analysis; surface losses and gas damping are also estimated. The reproducibility of the measurements of total losses is also discussed and the setup capabilities for measuring additive losses contributed by thin films deposited on the wafers or bonding layers. For instance, assuming that additive losses are due to an 80-nm-thick wafer bond layer with Young modulus about ten times smaller than that of silicon, we achieve a sensitivity to bond losses at the level of 5x10(-3) at 4 K and at about 2 kHz.     

Warping of silicon wafers subjected to back-grinding process

This study investigates warping of silicon wafers in ultra-precision grinding-based back-thinning process. By analyzing the interactions between the wafer and the vacuum chuck, together with the machining stress distributions in damage layer of ground wafer, the study establishes a mathematical model to describe wafer warping during the thinning process using the elasticity theory. The model correlates wafer warping with machining stresses, wafer final thickness, damage layer thickness, and the mechanical properties of the monocrystalline silicon. The maximum warp and the warp profile are measured on the wafers thinned to various thicknesses under different grinding conditions, and are used to verify the modeling results.     

硅微陀螺仪器件级真空封装

为实现硅微陀螺仪真空封装以提高其性能,对硅微陀螺仪器件级真空封装技术进行研究.首先,设计硅微陀螺仪的专用陶瓷封装管壳,并采用钎焊技术进行封帽,采用金锑合金为焊料以满足封装过程中的高温.分析除气工艺对硅微陀螺仪品质因数的影响,除气试验结果表明,将硅微陀螺仪芯片和封装壳体放置在真空炉中进行高温烘烤,能有效地提高硅微陀螺仪的品质因数.制定硅微陀螺仪器件级真空封装的工艺流程,封装好的硅微陀螺仪的品质因数约为10 363.7,约为空气下的50倍.硅微陀螺仪品质因数跟踪测试结果表明,真空封装的硅微陀螺仪存储5个月后,其品质因数降低为最初的55.1%,这表明采用该器件级真空封装技术封装的硅微陀螺仪的真空保持度较差,有待进一步研究.