基于InP HBT的5 GS/s采样保持电路设计

基于0.7μm、ft=280 GHz的InP HBT工艺设计了一种双开关宽带超高速采样保持电路。芯片面积1.5 mm×1.8 mm,总功耗小于2.1 W。仿真结果表明,电路可以在5 GS/s采样速率下正常工作。当采样速率分别为5 GS/s和1 GS/s时,在输入信号功率为4 d Bm的情况下,采样带宽分别为16 GHz和20 GHz;在输入信号功率为4 d Bm且其频率小于5 GHz的情况下,电路的SFDR分别不低于43 d Bc和50 d Bc。     

一种40 GSa/s超宽带采样保持电路

基于0.7μm的InP双异质结双极晶体管（DHBT）工艺设计了一种超高速宽带采样保持电路。输入缓冲器采用Cherry-Hooper结构有效提升了电路的增益和带宽。时钟缓冲器采用多级Cascode结构提升时钟信号的带宽。芯片面积1.40 mm×0.98 mm，总功耗小于1.1 W。测试结果表明：电路可以在40 GSa/s采样速率下正常工作。电路的-3 dB带宽在采样态为24 GHz，在采样保持态为19 GHz。在采样保持态，当输入4 GHz、-6 dBm信号时，电路的总谐波失真（THD）低于-41.5 dBc，有效位数（ENOB）相当于6.6。时域测试波形在本文也有呈现。     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

一种可编程的2.4GHz CMOS多模分频器

采用0.35μm CMOS工艺设计并实现了一种多模分频器.该多模分频器由一个除4或5的预分频器和一个除128～255多模分频器在同一芯片上连接而成;在电路设计中,分析了预分频器功耗和速度之间的折中关系,根据每级单元电路的输入频率不同对128～255多模分频器采用了功耗优化技术;对整个芯片的输入输出PAD进行了ESD保护设计;该分频器在单端信号输入情况下可以工作到2.4GHz,在差分信号输入下可以工作到2.6GHz以上;在3.3V电源电压下,双模预分频器的工作电流为11mA,多模分频器的工作电流为17mA;不包括PAD的芯片核心区域面积为0.65mm×0.3mm.该可编程多模分频器可以用于2.4GHz ISM频段锁相环式频率综合器.     

可调节型低抖动时钟占空比稳定电路的设计

介绍了一种用于高速流水线ADC双沿采样的时钟占空比稳定电路。在传统占空比稳定电路的基础上,增加含连续时间积分器的反馈环路,并设计了时钟周期检测电路,同时可通过SPI配置积分器的参考电压,在片外调节芯片制造过程中产生的误差,并在前端增设一个高增益带宽时钟放大器,用来放大幅度很小(Vp-p100mV)的差分输入时钟信号。电路采用0.18μm 1.8V 1P5MCMOS工艺,可对频率范围为50~250MHz、占空比范围为10%~90%的输入时钟进行稳定调节,时钟峰-峰值抖动约为0.3ps@250MHz。     

一种用于天文望远镜的低噪声CCD读出电路

设计了一种用于天文望远镜的低噪声电荷耦合器件(Charge Coupled Devices,CCD)读出电路.该读出电路主要包括电容增益电路、单端转差分电路、双斜率积分电路以及缓冲器电路.CCD读出电路采用SMIC 0.18μm1P6M CMOS工艺实现.后仿真结果表明,在电源电压3.3V,输入信号67kHz,输出信号80mV峰值时,输出信号动态范围86dB,等效输入噪声2.523nV/Hz1/2,整体功耗1.25mW.     

一款具有新颖的采样保持电路应用于脉冲式超宽带技术的欠采样型模数转换器

本文提出了一款基于CMOS 0.13um,具有新颖的采样保持电路,应用于脉冲式超宽带接收机的欠采样型模数转换器.本文主要的难点在于实现拥有远远高于奈奎斯特频率的输入信号的欠采样型模数转换器。根据我们的了解,本文是当今第二次提出当采样时钟大约在1.056GHz,输入信号超过4GHz的欠采样型模数转换器。电路设计中,我们提出了一款新颖的采样保持电路,解决了信号幅度的衰减和高频输入信号线性度的问题。一款使用零静态功耗动态失调校准比较器被进一步优化,实现了失调,速度以及功耗的要求。测试结果显示,当采样频率为1.056GHz,输入信号高达4.2GHz时,SFDR 为30.1dB。不包括缓冲器,ADC的功耗为30mW,芯片面积为0.6mm2.ADC的FoM是3.75pJ.     

12Gb/s 0.25μm CMOS数据判决和1∶2数据分接电路

采用TSMC 0.25μm CMOS工艺成功实现了用于光纤传输系统的12Gb/s数据判决和1∶2数据分接电路.测试结果显示,在3.3V电源供电情况下,功耗为600mW,其中包括3路输出缓冲.输入信号单端峰峰值为250mV时,该芯片的工作速率超过12Gb/s,相位裕度超过100°.芯片面积为1.07mm×0.99mm.     

12Gb/s 0.25μm CMOS数据判决和1∶2数据分接电路

采用TSMC 0.25μm CMOS工艺成功实现了用于光纤传输系统的12Gb/s数据判决和1∶2数据分接电路.测试结果显示,在3.3V电源供电情况下,功耗为600mW,其中包括3路输出缓冲.输入信号单端峰峰值为250mV时,该芯片的工作速率超过12Gb/s,相位裕度超过100°.芯片面积为1.07mm×0.99mm.     

脉冲激光多回波峰值检测电路设计

在脉冲激光探测中，常采用峰值检测电路获取强度信息。当激光通过部分反射或部分遮挡的空间多层物体时，会产生多个回波。传统峰值检测电路无法准确探测多回波峰值。因此，基于脉冲多回波峰值检测原理，设计了一种具有高集成度的新型脉冲多回波峰值检测电路芯片。该芯片以两级峰值采样保持电路结构为基础，通过采用交织采样和多路复用技术优化了电路结构，实现了对多回波信号的峰值检测。芯片采用CMOS 0.18μm工艺设计，面积约为2.6 mm×0.48 mm，测试结果表明，所设计的芯片能够有效检测幅值范围50～500 mV、脉宽5 ns的多回波信号，峰值输出电压的最大误差为4.8%，通道间的输出电压最大相对偏差为5.7%，具有更精细的多回波探测能力，可集成应用于脉冲激光探测系统。     

80 Gb/s 2 : 1 multiplexer in 0.13-μm SiGe BiCMOS technology

This work presents an ultra-high speed 2 : 1 multiplexer (MUX) in a SiGe BiCMOS technology with fT = 103 GHz. To boost the operating speed, the system scheme is optimized including a 2 : 1 selector circuit directly driving an external 50 Ω load, and two wide-band data buffers and one clock buffer in the input stage. The chip exhibited an open eye at 80 Gb/s with a 160 mV single-ended voltage swing.     

基于0.13微米锗硅BiCMOS工艺的80 Gb/s 2:1 复接器

本文介绍了基于0.13微米锗硅BiCMOS工艺设计的超高速2:1复接器芯片,工艺fT为103 GHz。为了最大限度提高工作速度,系统方案进行了优化,采用了选择器输出直接驱动片外50 Ω负载的形式,并在输入级集成了两个宽带数据放大器和一个时钟放大器。经测试,芯片输出眼图达到了80 Gb/s的速率,单端电压摆幅为160 mV。     

Design of Ka-band antipodal finline mixer and detector

This paper mainly discusses the analysis and design of a finline single-ended mixer and detector. In the circuit, for the purpose of eliminating high-order resonant modes and improving transition loss, metallic via holes are implemented along the mounting edge of the substrate embedded in the split-block of the WG-finline-microstrip transition. Meanwhile, a Ka band slow-wave and bandstop filter, which represents a reactive termination, is designed for the utilization of idle frequencies and operation frequencies energy. Full-wave analysis is carried out to optimize the input matching network of the mixer and the detector circuit using lumped elements to model the nonlinear diode. The exported S-matrix of the optimized circuit is used for conversion loss and voltage sensitivity analysis.The lowest measured conversion loss is 3.52 dB at 32.2 GHz; the conversion loss is flat and less than 5.68 dB in the frequency band of 29-34 GHz. The highest measured zero-bias voltage sensitivity is 1450 mV/mW at 38.6 GHz,and the sensitivity is better than 1000 mV/mW in the frequency band of 38-40 GHz.     

A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology

This paper presents a 6-b 12-GSample/s track-and-hold amplifier (THA) fabricated in an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT) technology. The THA is intended for the front end of a high-speed analog-to-digital converter in a digital-based electronic polarization-mode dispersion compensation circuit for a 10-Gb/s optical receiver. With a high-speed switched emitter follower and clocked track-to-hold transition operation, it shows the signal bandwidth over 14 GHz and features a total harmonic distortion (THD) compatible with 6-b operation with input frequency of 6 GHz and a sampling frequency of 12 GHz. The THD increases better than -23 dB with a 12-GHz input signal of 1 V/sub pp/, corresponding to a 4-b resolution, under a differential clock of 12 GHz.     

5-bit, 10 GSamples/s track-and-hold circuit with input feedthrough cancellation

Input signal feedthrough in a high-speed track-and-hold (T/H) circuit often degrades the performance of analogue-to-digital data converters. A 10 GSamples/s CMOS T/H circuit with input feedthrough cancellation is proposed. This T/H circuit has been fabricated in 0.18 /spl mu/m CMOS process. It achieves 5-bit resolution in 2.5 GHz analogue input signal at 10 GSamples/s.     

280 W output power single-ended amplifier using single-die GaN-FET for W-CDMA cellular base stations

A single-ended amplifier using a single-die GaN-FET was successfully developed for W-CDMA cellular base-station systems. The developed amplifier delivers a peak saturated output power of 280 W with a linear gain of 12.6 dB at a drain voltage of 48 V under 2.15 GHz 3GPP W-CDMA signal input. It is believed that the 280 W output power is the record output power in single-ended amplifiers at 2 GHz band. A high drain efficiency of 29% is also obtained at 8 dB power back off from the saturated output power.     

Millimeter-wave wide-band amplifiers using multilayer MMICtechnology

This paper describes millimeter-wave wide-band single-ended and balanced amplifiers using novel multilayer monolithic microwave/millimeter-wave integrated circuit (MMIC) technology. The fundamental characteristics of thin-film transmission lines and a 50-GHz-band multilayer MMIC directional coupler are described through measurements up to 60 GHz. A single-ended amplifier fabricated in a 1.1 mm×0.8 mm area, shows a gain of about 12 dB with a noise figure of better than 5 dB around 50 GHz. A balanced amplifier fabricated using the multilayer MMIC directional couplers and single-ended amplifiers, shows a gain of 10-17 dB with input and output return losses of better than 14 dB from 33 to 53 GHz. The transmission lines and directional couplers can be effectively combined with millimeter-wave active circuits without degrading the circuit performance or increasing the circuit area. To our knowledge, these are the first millimeter-wave active circuits employing multilayer MMIC technology     

Ku-band subsampling track-and-hold amplifier with 8 ENOB resolution

A wideband subsampling track-and-hold amplifier has been designed for input frequencies up to Ku-band and clock rates up to 2.5 GS/s. Circuits were fabricated in 1 /spl mu/m InP SHBT technology. Spur-free dynamic range measured with two-tone input frequencies of 12.6 and 12.602 GHz and a 2.5 GS/s clock rate ranges from 53-69 dB at an input level of -1 dBFS for each tone. Signal-to-noise ratio (SNR) test results show that the master/slave (M/S) track-and-hold design provides 59 dB of SNR in a 1 GHz bandwidth at input frequencies up to at least 2.6 GHz. A single track-and-hold dissipates 1.5 W while the M/S configuration dissipates 2.5 W.     

96-GHz static frequency divider in SiGe bipolar technology

A static frequency divider designed in a 210-GHz f/sub T/, 0.13-/spl mu/m SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).     

Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection

In this paper, the locking range of the injection-locked ring oscillators is investigated. To improve the injection efficiency and the locking range for superharmonic frequency division, a multiple-injection technique is proposed. Using a 0.18-mum CMOS process, a wideband frequency divider based on a three-stage ring oscillator is implemented for demonstration. With a tunable free-running frequency, the fabricated circuit provides 2:1 and 4:1 frequency division with a single-ended input signal ranging from 13 to 25 and 30 to 45 GHz, respectively. Compared with the case of the single-ended injection, the locking range of the frequency divider almost doubles when multiple-input injection with optimum phases is utilized. The experimental results exhibit good agreement with the theoretical derivation and the circuit simulation.