基于虚拟控制器的多任务断点调试器设计与实现

随着多任务控制器的出现及算法逻辑的复杂程度逐渐提高,常规的虚拟控制器难以实现多任务模拟,且逻辑调试方法单一,难以保证逻辑的正确性。提出一种多任务断点调试器设计方案,将运算任务抽象为结构实体,并定义运算任务运行状态,通过两级任务控制块控制任务状态转换过程,进而实现多运算任务调度及单步、单页、单指令、自定义断点等调试功能,方便获取逻辑运算过程中的任意断面数据。将多任务断点调试器集成于虚拟控制器中,经功能验证后应用于实际工程调试,提高了算法逻辑质量,降低了现场调试周期和调试成本,确保现场控制的可靠运行。     

嵌入式处理器在片调试功能的设计与实现

以龙芯1号处理器为研究对象,探讨了嵌入式处理器中在片调试功能的设计实现方法.通过扩充IEEEP1149.1协议的JTAG测试访问端口（TAP）,并在处理器内部增加控制模块,实现了软件调试断点、调试中断、硬件断点以及单步执行等多种在片调试功能.调试主机只需要通过一根JTAG调试电缆就可以访问目标处理器内部寄存器等各种资源,并控制目标处理器的运行过程,实现了处理器的在片调试功能,大大地方便了软件开发与系统调试.     

一种新的嵌入式处理器在线调试方法

针对嵌入式处理器在FPGA中的应用现状,通过引入通用的调试模块,实现了对没有调试接口的嵌入式处理器进行在线调试的功能。所设计的调试模块通过引入专用的调试中断及与之对应的调试服务程序实现一种处理器响应断点（breakpoint）的机制,并基于双端口RAM中一种巧妙的地址映射机制实现同时对多行代码设置断点的功能。实际的工程应用情况表明,新的调试方法扩展了对小型嵌入式处理器进行调试的手段,明显提高了开发效率。     

多核处理器YHFT-QDSP的调试系统

YHFT-QDSP是一款多核处理器。为满足其并发调试和实时调试的需要,在原有单核调试系统的基础上设计实现了多核同步调试系统和片上实时追踪系统（片上Trace）。多核同步调试提供了命令广播和断点同步触发等并发程序协同调试的功能;片上Trace通过专用硬件记录程序执行路径和数据读写等信息实现非入侵实时调试。本文从原理、结构和
软硬件实现等方面介绍了该调试系统。     

基于uVision2的单片机实验系统仿真

uVision2是标准的Windows应用程序,该集成开发环境包含:编译器、汇编器、实时操作系统、调试器等,支持汇编、C语言编译。uVision2调试功能强大,具备源极调试、符号调试及历史跟踪、复杂断点等功能。 通过它可以产生外部中断,更新模拟输入,将串行数据送入片内串行口,从而仿真外部硬件,以软件代替单片机实验所需的硬件。另外在调试过程中,可实时跟着变化随时观察结果。因此用uVision2作为仿真软件开发平台能大大地提高开发的效率。     

一种工业控制器的组态调试器实现方法

在工业过程控制领域,常常需要对控制器内的复杂控制逻辑进行单步执行、断点调试,以便明确诊断逻辑的正确性和合理性,但目前各厂家的工业控制器并不具备该功能。为了解决该问题,对高级编程语言C/C++的调试器功能进行了系统的研究,包括其程序断点的设计原理和调试器的实现机制。结合工业控制器算法组态的语言特点,设计了一种面向算法组态的调试器,并将其运用到工业控制器的嵌入式软件系统中。通过与算法逻辑运算单元的交互设计,成功实现了复杂控制逻辑的单步执行、逐页逐模块以及断点调试等功能。试验结果表明,集成组态调试器功能的工业控制器,能够极大地方便项目实施过程中的现场组态和深入调试,有效降低组态算法的错误率和提高工程调试的效率。该控制器为工业控制器的全方位诊断功能以及虚拟仿真的实现提供了一定的参考。     

嵌入式远程调试工具的研究与实现

在嵌入式软件开发中,调试是一个重要的环节,调试工具是衡量软件开发环境优劣的重要因素.本文对插桩方式的嵌入式远程调试工具进行了分析与研究,采用GNU gdb远程串口通信协议,通过软件接管目标系统的全部异常实现对目标程序的调试与跟踪,实现读/写内存与寄存器、设置断点、单步执行和继续执行功能,并应用于基于ARM的RTEMS嵌入式实时操作系统与应用程序的调试中.     

面向VLIW DSP结构的编译器的设计与实现

VLIW编译器实现指令并行性挖掘、相关性检查、指令调度等职能,对VLIW处理器的性能影响较大.本文基于一款VLIW DSP芯片,利用可重定位编译器IMPACT的前端和代码生成器模板,设计和实现了高性能的VLIW编译器.利用伪数据类型和Intrinsic函数结合,在编译器中构建了对SIMD功能的支持.实验结果显示,对比基于GCC版本的编译器,该编译器生成的指令数平均下降42%,并行包数下降30%.     

可复用微处理器片上调试功能的设计与实现

为了方便软件与应用系统的开发与调试,提出一种可复用的微处理器片上调试方法.通过设计通用的调试指令集和增加调试模块,并扩展处理器内核功能,实现了断点设置与取消、内核运行的流水级精确控制、内核资源访问、任意程序段运行中特殊事件的统计等片上调试功能.该方法已在自主研发的SuperV_EF01 DSP上实现.在CMOS 90 nm 工艺下的综合结果表明,新增的片上调试功能不影响SuperV_EF01 DSP的关键路径时序,而芯片总面积仅增加了3.87％.     

GCC编译器到Trimedia的移植

重点分析介绍了GCC编译器源代码的结构和程序的主要函数功能.并据此提出了移植GCC编译器到多媒体处理器Trimedia的一个方案及介绍了其实现的重点.     

工序可间断的资源均衡分析

针对网络计划资源均衡问题,提出了一种新型的工序可间断的资源均衡模型,并在模型中引入一些工序间断率、间断延期率等无量纲变量来处理工序可间断的情况。这些变量使得模型中各工序间的时间约束关系在求解过程中能自动得到满足,从而避免不可行解的出现。该模型还兼容了不可间断资源均衡模型的功能,并可以处理特殊工序不可间断的要求。通过采用遗传算法对本文的模型进行求解,验证了模型的有效性。     

YH-2C语言优化编译器的设计

Ｃ语言优化编译器是借助于微机上的Ｉｎｔｅｌ８０３８６Ｃ语言编译器为研制平台，采用交叉编译的方法设计实现的，它是我国自行设计的第一个从底层开发实现的巨型机Ｃ语言编译器。本文首先给出了ＹＨ－２Ｃ语言优化编译器的设计原理，然后详细介绍了其主要系统组成和技术特点，最后指出了我们以后进一步要做的工作     

可视编译器的设计与实现

通过一个实际的可视编译器开发实例,描述编译器前端的实现方法。这个编译程序除了易于操作的窗口程序外,还包含了标准C语言子集的编译器。这套编译器涵盖了词法分析器、语法分析器、语义分析器、中间代码生成器和简单错误处理器等一整套程序。通过这个实例可以直观地表现词法和语法的构造过程,图文并茂,生动说明编译器中词法器、语法器的功能及其构造过程。     

Ytracc: A parse browser for yacc grammars

We describe a program for the display and exploration of complex, domain-specific information: ytracc, an interactive grammar debugging tool for compiler writers. The ytracc system provides the designer of a yacc grammar a method of tracing a parser as it uses the grammar, ytracc captures the states of the parse as it is carried out. The captured parse can then be replayed forwards or backwards, step-by-step, or subtree-by-subtree, as defined by the non-terminals of the grammar. The tool has been successfully used by students as an assistant in an advanced undergraduate compiler construction class, and we use the tool in our everyday work.     

On the automatic parallelization of the Perfect Benchmarks(R)

This paper presents the results of the Cedar Hand-Parallelization Experiment conducted from 1989 through 1992, within the Center for Supercomputing Research and Development (CSRD) at the University of Illinois. In this experiment, we manually transformed the Perfect Benchmarks(R) into parallel program versions. In doing so, we used techniques that may be automated in an optimizing compiler. We then ran these programs on the Cedar multiprocessor (built at CSRD during the 1980s) and measured the speed improvement due to each technique. The results presented here extend the findings previously reported. The techniques credited most for the performance gains include array privatization, parallelization of reduction operations, and the substitution of generalized induction variables. All these techniques can be considered extensions of transformations that were available in vectorizers and commercial restructuring compilers of the late 1980s. We applied these transformations by hand to the given programs, in a mechanical manner, similar to that of a parallelizing compiler. Because of our success with these transformations, we believed that it would be possible to implement many of these techniques in a new parallelizing compiler. Such a compiler has been completed in the meantime and we show preliminary results     

Experience with the universal intermediate language janus

Janus is a symbolic language intended for use as an intermediate language in the transportation of software. Since its initial design four years ago, it has been used to implement a portable Pascal compiler, in the design of an Algol 68 compiler, and to realize a portable package of mathematical routines. These experiences, together with a critical re-evaluation of the design criteria, have led to some modification of the specifications of Janus and an increased confidence in the viability of the approach. They have also indicated some problems yet to be solved. This paper reviews the significant lessons which we have learned, and quotes some results which support our confidence.     

Action semantics-directed prototyping

We present a methodology for compiler synthesis based on Mosses-Watt's action semantics. Each action in action semantics notation is assigned specific “analysis functions”, such as a typing function and a binding-time function. When a language is given an action semantics, the typing and binding-time functions for the individual actions compose into typing and binding-time analyses for the language; these are implemented as the type checker and static semantics processor, respectively, in the synthesized compiler. Other analyses can be similarly formalized and implemented. We show a sample language semantics and its synthesized compiler, and we describe the compiler synthesizer that we have developed.     

基于GCC关键变量数据流分析算法的程序切片技术

随着程序的规模的扩大和复杂度的提高,通过直接分析源码进行程序切片,变得十分困难。在现有的利用编译优化技术来优化程序切片的方法中,存在无法有效利用程序的编译时信息和编译器的优化技术,以及对语言的支持不完善的问题。为此,分析了GCC编译器在编译时的中间表示,首次提出了基于GCC关键变量数据流分析算法的程序切片技术,以程序的GIMPLE中间表示为基础,以程序基本块为单位,通过迭代求解数据流方程,分析程序基本块内和不同基本块间的关键变量数据流信息。该程序切片技术可以获取源程序中仅与预设目标函数相关的关键变量和关键语句,缩减程序规模。最后通过实验,证明了该算法的可行性。     

Barycentric parameterizations for isotropic BRDFs

A bidirectional reflectance distribution function (BRDF) is often expressed as a function of four real variables: two spherical coordinates in each of the "incoming" and "outgoing" directions. However, many BRDFs reduce to functions of fewer variables. For example, isotropic reflection can be represented by a function of three variables. Some BRDF models can be reduced further. In This work, we introduce new sets of coordinates which we use to reduce the dimensionality of several well-known analytic BRDFs as well as empirically measured BRDF data. The proposed coordinate systems are barycentric with respect to a triangular support with a direct physical interpretation. One coordinate set is based on the BRDF mode) proposed by Lafortune. Another set, based on a model of Ward, is associated with the "halfway" vector common in analytical BRDF formulas. Through these coordinate sets we establish lower bounds on the approximation error inherent in the models on which they are based. We present a third set of coordinates, not based on any analytical model, that performs well in approximating measured data. Finally, our proposed variables suggest novel ways of constructing and visualizing BRDFs.     

Lex和yacc在Delphi中的应用

本文介绍如何在Delphi中利用专用工具lex和yacc创建简单编译器的过程。并给出一个简单的自定义可视化编译器的制作实例。