Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2m double-poly p-well process through MOSIS.     

Bulk-drain connected load for subthreshold MOS current-mode logic

Bulk-drain connected PMOS transistors are proposed as loads for subthreshold MOS current-mode logic gates. Such loads exhibit an approximately linear dependence of the subthreshold drain-source current on the drain-source voltage, guaranteeing robust gate operation. The design and performance of an inverter gate and ring oscillator in a 0.25 mum CMOS technology are presented     

MOS triangle-to-sine wave convertor based on subthreshold operation

A novel MOS triangle-to-sine wave convertor (TSC) is proposed. The novel circuit is based on the exponential characteristics of MOS devices operated in the subthreshold region. The circuit with a total harmonic distortion of 0.21% and bandwidth of 100 kHz has been demonstrated by PSPICE simulation and experiments.<>     

An effect of the subthreshold current on scaled-down MOS dynamic RAMs

Data-output holding characteristics of MOS dynamic RAMs with 2.5 /spl mu/m design rules are studied by employing the hidden-RAS-only-refresh mode. It is verified that the noise voltage caused by internal circuit operation increases the subthreshold current and that the clamp circuitry effectively decreases the subthreshold current.     

Novel high PSRR high-order temperature-compensated subthreshold MOS bandgap reference

Novel high power supply rejection ratio (PSRR) high-order temperature-compensated subthreshold metal-oxide-semiconductor (MOS) bandgap reference (BGR) is proposed in Semiconductor Manufacturing International Corporation (SMIC) 0.13 μm complementary MOS (CMOS) process. By adopting subthreshold MOS field-effect transistors (MOSFETs) and the piecewise-curvature temperature-compensated technique, the output reference voltage's temperature performance of the subthreshold MOS BGR is effectively improved. The subthreshold MOS BGR achieves high PSRR performance by adopting the technique of pre-regulator. Simulation results show that the temperature coefficient (TC) of the subthreshold MOS BGR is 1.38×10^?6/°C when temperature is changed from ?40 °C to 125 °C with a power supply voltage of 1.2 V. The subthreshold MOS BGR achieves the PSRR of ?104.54 dB, ?104.54 dB, ?104.5 dB, ?101.82 dB and ?79.92 dB at 10 Hz, 100 Hz, 1 kHz, 10 kHz and 100 kHz respectively.     

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400µm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, edge, striation, and gradient effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

On the temperature dependence of subthreshold currents in MOS electron inversion layers

It has been observed that the “n” factor which enters into the exponential dependence of drain current on gate voltage for MOS transistors operating in the weak inversion region, exhibits a significant temperature dependence. This effect is correlated with the increase of interface state density towards the band edges and the variation of the space-charge capacitance.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

Current-mode signal processing implementation in HV SoI integrated systems

The paper presents and discusses possibilities and potential of current-mode based signal processing in high-voltage (HV) integrated systems, including current-mode functional block implementation into signal path of HV voltage-mode circuits. The paper is mostly focused on analog circuitry, implemented with the use of SoI processes. Discussion is based on the range of circuit solutions previously devised by authors and presently combined to present cumulated potential of current-mode approach in high-voltage (HV) integrated circuits. Analysis of the referenced research conducted by the authors of the paper, points out that in HV integrated systems, there are application areas well suited for current-mode processing implementation rather than the classic voltage-mode approach. Simplicity and consistency of HV current-mode functional blocks are presented, along with fitness of current-mode circuits for convenient implementation into HV SoI integrated circuits, with very limited loss of operation quality as compared to corresponding low-voltage functional blocks. Means of implementing current-mode circuits into HV voltage-mode systems are discussed.     

The MOS implementation of low-speed modems

This paper identifies the improvements due to large-scale integration [LSI] in the areas of cost, performance, size, reliability, and testing of data communication equipments. An example using Motorola's MC6860 Digital Modem is given. Techniques for implementing linear functions using digital designs and processing methods are discussed along with future technology trends and projections.     

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

The authors present a parametric model which covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel-length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.     

A parametric short-channel MOS transistor model for subthreshold and strong inversion current

A parametric model with short-channel capabilities is presented for MOS transistors. It covers the subthreshold and strong inversion regions with a continuous transition between these regions. The effects included in the model are mobility reduction, carrier velocity saturation, body effect, source-drain resistance, drain-induced barrier lowering, and channel length modulation. The model simulates accurately the current characteristics as well as the transconductance and output conductance characteristics which are important for analog circuit simulation.     

Digital implementation of the Q-C method for MOS measurements

Computer controlled hardware and software needed for digital implementation of the Q-C method are described. Incorporation of a program that generates ideal data permits debugging and complete verification of the analysis routines. An error sensitivity check shows the parameters that must be measured most carefully are the device area, oxide capacitance, and the voltage independent capacitance in series with the MOS capacitor. The digital technique was found to provide advantages in convenience, speed, accuracy and versatility when implementing the Q-C method.     

Improved subthreshold characteristics of n-channel MOS transistorsfabricated in solid phase epitaxially regrown silicon-on-sapphire films

Subthreshold characteristics of n-channel silicon-on-sapphire (SOS) MOSFETs have been measured following solid-phase epitaxial regrowth of the epitaxial film. Results obtained from planar n-channel transistors show that an increase in the subthreshold current slope can be obtained by improving the quality of the silicon layer. These results are explained in terms of a reduction in the density of interface traps present at the Si/SiO₂ interface     

Correlation-based associative memory and its MOS implementation

We propose an associative memory based on minimization of a free-energy function determined by the library vectors to be stored. When the library vectors are bipolar, the energy function contains minima at the library vector location. The minima can be sought by search techniques such as gradient descent. Significantly, if the correlation nonlinearity is chosen to be sufficiently strong, then convergence occurs in a single step. We demonstrate how the algorithm can be implemented using MOS circuitry.     

Application of the difference subthreshold swing analysis to studygeneration of interface traps in MOS structures due to Fowler-Nordheimaging

Peaks in difference subthreshold swing relaxation defined as a function of the electron fluence yield generation cross sections and the densities of generated interface traps. The simple mathematical theorem, on which our measurements depend, has been proven experimentally. This technique has the advantage of being direct, fast and convenient; it is appropriate for the study of complex interface trap generation phenomena. The experiment shows that the interface traps generated consist of two kinds with different generation cross sections under high field stresses     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.