一种新型的单面蚀刻技术制备埋容电路板

介绍了一种新型的埋入电容电路板的单面蚀刻工艺。本工艺主要针对介质层厚度≤50μm的埋入电容材料,在制作单面图形时,不去掉未曝光一面的干膜及干膜保护膜,棕化后再过显影线将干膜去掉。对该工艺可行性进行了评估,并验证了其可靠性。实验结果表明,采用此工艺可以减少工艺难度,加工成本降低了3%,且产品合格率达86%以上。     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

激光直接成像技术（V）—化学镀Sn和直接覆铜板上的LDI

4 在化学镀锡上的LDI 这是指经制备的在制板铜箔上涂覆上一层厚度为0.8/μm的锡箔,接着通过UV激光蚀去不需要的锡镀(涂)层及其底下的铜箔厚度3～5μm所形成的图形,最后以锡层为抗蚀剂进行碱性蚀刻(如常规的碱性CuCl_2蚀刻液),便可得到所期望的精细导体图形。     

RTR（Roll to Roll）方式制作25μm／25μmCOF精细线路的参数优化

随着电子产品小型化和液晶显示器IC封装技术的快速发展,COF（Chipon Film）技术的应用市场得到了迅速扩大。按照片式减成方法制作的线宽／线距在50μm／50μm以下的精细线路,常常会出现导线过细或断线等缺陷。论文采用目前先进的RTR（Roll to Roll）生产工艺,选用12μm钢箔、15μm干膜,使用玻璃菲林进行图形转移,并运用正交设计法对影响精细线路品质的曝光能量、显影速度、蚀刻速度、蚀刻压力等因素进行优化试验。以精细线路的线宽和蚀刻系数作为评价标准,找出最佳参数,并分析了蚀刻压力对精细线路的影响机理。将最优化参数应用到生产中,使25μm／25μm的COF精细线路的成品率提高20％。最终实现25μm／25μm的COF精细线路的小批量生产。     

激光直接成像技术(Ⅴ)--化学镀Sn和直接覆铜板上的LDI

4 在化学镀锡上的LDI 这是指经制备的在制板铜箔上涂覆上一层厚度为0.8μm的锡箔,接着通过UV激光蚀去不需要的锡镀(涂)层及其底下的铜箔厚度3～5μm所形成的图形,最后以锡层为抗蚀剂进行碱性蚀刻(如常规的碱性CuCl2蚀刻液),便可得到所期望的精细导体图形.     

COF（Chip on Film）30μm／30μm精细线路的研制

近年来,随着驱动IC的I/O数量日益增多,芯片I/O端的排列密度也越来越大。为了与间距日益精细的芯片I/O端相适应,COF基板的线宽/间距已经普遍降到50μm以下,尤其是某些内部引线键合(ILB)端,其线宽/间距已经减小到15μm。由于传统的减成法存在不可避免的侧蚀问题,所以用它来制作如此精细的线路存在一定难度。但是使用半加成法就能很大程度的抑制侧蚀现象,它更适合于制作非常精细的线路。文章中,介绍以铜箔厚度仅有2μm的溅射型挠性覆铜板为原材料,采用半加成法制作了最小线宽/间距分别为50μm/50μm和30μm/30μm的精细线路基板。在半加成法的差分蚀刻工艺中,选用硫酸/双氧水蚀刻液来蚀刻去除基材铜,而不是选用常用的盐酸/氯化铜蚀刻液。结果表明,半加成法具有很好的蚀刻性能,其制作出的线路横截面非常接近矩形。即使基板的线宽/间距由50μm/50μm下降到30μm/30μm,线路的横截面依然非常理想,并没有出现向梯形变化的趋势。同时,由于半加成法所需的蚀刻时间非常短,它能很好的保持线宽,使其与设计尺寸一致。     

浅谈埋电容PCB的制作工艺

埋电容技术作为PCB制作的一种新工艺。PCB内埋电容不仅节省了PCB板面空间,同时还大量减少了PCB板面SMT焊点数目,提高了PCB板件的可靠性。因目前市场上推出的埋电容材料,由于芯板较薄,通常介质层厚度≤50μm,薄芯板的特性使材料在PCB加工过程中存在一定的难度。本文选用一种陶瓷粉填充的埋电容材料,对该种材料制作埋电容的PCB加工工艺进行相关的研究。     

脊形波导激光器中GaInP／AlGaInP选择蚀刻性的研究

本文制作了670nmGaInP/AlGaInP应变层量子阱脊形波导激光器,为了进一步优化工艺,在普通的单量子阱材料横向结构中嵌入30－50nm的GaIlP蚀刻阻挡层,用此种材料加工而成的控长1200μm,宽64μm的氧化条激光器的阈值电流密度为340A／cm^2,采用配比为1．0：2．5的HCl:H2O深液对GaInP/AlGaIn进行湿蚀刻研究,得到了较好的选择恂刻性结果。     

新产品与新技术（36）

精细线路用抗蚀干膜的新动向 日本旭化成公司针对PCB高密度化,推出精细线路用抗蚀干膜系列产品。有激光直接成像用ADH系列干膜,其中供减成法蚀刻工艺的干膜厚度1μm,最小线路解像度L/S=12μm/12μm;供半加成法图形电镀工艺的干膜厚度25μm,     

用湿化学蚀刻法制作短腔GaAlAs激光器

用一种新的化学蚀刻方法制出了短腔(GaAl)As条形激光器,此激光器的阈值电流为30mA。该方法使用了一多层金属掩膜。激光器腔长23μm、宽12μm,且在蚀刻端面没镀反射膜。在脉冲条件下获得了准单模输出。     

基于新型介电弹性体平行板电容器的研究

为了研究具有传感功能的可变电容器,采用新型介电弹性体材料制成平行板电容器。研究了该电容器充放电前后的外形变化及影响电容大小的因素。结果表明:在高压充放电前后,电容器的极板面积和两电极板间距离都发生了明显的变化;电容随着外加电压的增大而增大;在外加电压为6 000 V的条件下,电容随着材料预拉伸的增大出现一极大值,随后又减小,即在变化过程中存在拐点;另外,电容器的电极材料用石墨粉时要比用导电胶时电容大。     

A novel sub-half micron Al-Cu via plug interconnect using lowdielectric constant material as inter-level dielectric

A novel Al-Cu via plug interconnect using low dielectric constant (low-ϵ) material as inter-level dielectric (ILD) has been demonstrated. The interconnect structure was fabricated by spin-on deposition of the low-ϵ ILD and physical vapor deposition (PVD) of the Al-Cu. Excellent local ILD planarization was achieved by a two-step spin-on coating process. The dielectric constant of the low-ϵ no is about 2.7, which leads to significant interconnect wiring capacitance reduction. For the first time, completely filled Al-Cu:0.5% plugs with nearly vertical sidewalls were fabricated in organic low-ϵ ILD. Excellent via fill was observed with via size down to 0.30 μm. Low via resistance and excellent via reliability have been observed     

SiLK dielectric planarization by chemical mechanical polishing

As the feature size of integrated circuits is driven to smaller dimensions the importance of the inter- and intralayer isolator capacitance in future metallization schemes becomes more pronounced. Organic polymers with low dielectric constants are one class of material choice for the replacement of SiO₂. However, their successful integration into functional circuits requires new fabrication procedures. The embedded dielectric scheme offers an evolutionary path for their successful integration into a subtractive etched, aluminum-based integrated circuit. This scheme can effectively lower the total capacitance while minimally changing the rest of the metallization fabrication process. However, the non-conformal deposition of spin-on polymers requires an effective planarization process. Therefore, this paper focuses on the planarization capability of a chemical mechanical polishing process (CMP) using SiLK resin as the interlayer dielectric material. The experimental results demonstrate the high planarization capability of the CMP process using a commercially available slurry. The post-CMP degree of planarization is greater than 95% for all feature dimensions and this planarity can be achieved rapidly. SiLK dielectric coatings are therefore considered as a promising candidate to replace SiO₂ in existing Al/W-based technologies.     

Embedded thin film capacitors-theoretical limits

The large physical size of capacitors and/or excessive values of associated lead inductance are two major limitations in the development of novel packaging modules, with high packaging density, high performance and reliability along with low system cost. Embedded capacitor technology in thin film form offers a promising solution to these limitations. A design space with capacitance density and breakdown voltage as performance properties, with material dielectric constant and film thickness as parameters has been explored, focusing on tantalum pentoxide (Ta/sub 2/O/sub 5/) as the dielectric material. An inherent tradeoff is established between breakdown voltage and capacitance density for thin film capacitors. The validity of the proposed design space is illustrated with thin films of Ta/sub 2/O/sub 5/, showing deviation from the "best can achieve" breakdown voltage for films thinner than 0.4 /spl mu/m and films thicker than 1 /spl mu/m.     

Use of gas as low-k interlayer dielectric in LSI's: Demonstrationof feasibility

Reduction of the wire capacitance in LSI's has become an issue of the utmost importance since the wire parasitic capacitance plays a significant role in determining both chip speed and power. Low dielectric constant materials such as SiOF (k=3.3) are already in use in manufacturing, while other materials with lower dielectric constants (k=2.0~3.0) are under development. Technology for further reduction of the dielectric constant, however, has not been reported so far. In this paper, we propose a gas-dielectric process that has the potential to achieve almost the minimum physically possible value for the dielectric constant: 1.0. The conceptual feasibility of the process is demonstrated, and basic process characterization data are presented. In addition, issues to be considered when integrating the proposed process into LSI manufacturing are identified, and work currently in progress addressing these issues is discussed     

单轴应力下热氧化SiO_2的介电电致伸缩系数研究

微机电系统和集成电路中常用的热氧化SiO2是各向同性材料,研究了其在单轴应力场中介电常数的变化规律。依据介质在自由和束缚两种边界条件下受到单轴应力作用产生的应变不同,从电动力学基本关系出发推导了各向同性电介质两种边界下的介电电致伸缩系数计算公式,表明介电电致伸缩系数是与电介质的初始介电常数、杨氏模量和泊松比有关的常数。计算得到热氧化SiO2薄膜在自由和束缚条件下的介电电致伸缩系数M12分别为-0.143×10-21和-0.269×10-21 m2/V2。搭建了基于三维微动台的微位移加载系统,测量了在单轴应力下微悬臂梁SiO2薄膜电容的变化,测量得到热氧化SiO2薄膜的M12为(-0.19±0.01)×10-21 m2/V2,表明实际SiO2薄膜介质层的边界条件处于自由和束缚之间。     

Influence of carbonaceous electrodes on capacitance and breakdown voltage for hybrid capacitor

This paper presents a new type of capacitor and deals with a hybrid approach where the advantages of two systems, dielectric capacitors and the ultracapacitor are combined. The objective is to increase the capacitance and the energy storage capability, while or at least preserving or decreasing the volume of the passive components. In this aim, the surface area and structural properties of ultracapacitor electrodes and the high dielectric strength of a polymer material are associated. The surface roughness of the carbonbased electrodes, namely (activated carbon—AC, and carbon nanotubes—CNTs), has a good impact on the capacitance. However, the surface roughness also depends on the composition of carbonaceous materials and so does the capacitance. Moreover, the choice of the dielectric material is the key parameter. The better the impregnation of the roughness is, the better is the increase of the capacitance.Since the final objective is to improve the electrical energy stored by the capacitor, the effect of surface roughness on the breakdown voltage is also evaluated.     

Conductive Carbon as a Novel Front-End Electrode Material for a Trench DRAM

We report on the electronic properties and application of conductive carbon as a novel front-end material. Conductive carbon is attractive due to its metallic properties, high thermal stability, compatibility to Si-based dielectrics, and the availability of a low-cost batch deposition process. Here, we utilize carbon instead of a polysilicon top electrode in a deep trench capacitor with SiON node dielectric. A capacitance gain of 10% is observed due to suppression of electronic depletion. Furthermore, the midgap work function of 4.4 eV leads to a reduction of leakage currents due to a higher tunneling barrier. This allows electric thinning of the dielectric for a total capacitance gain of 20%, compared to a polysilicon electrode, while maintaining excellent electronic reliability characteristics.      

Augmented Cell Performance of NO-Based Storage Dielectric by N$_2$ O-Treated Nitride Film for Trench DRAM

Owing to the delayed introduction of high-kappa storage dielectric for trench DRAM, a new technology to extend the existing NO storage dielectric becomes a prerequisite. For trench DRAM, the nitride film of NO-based storage dielectric has been proved to possess higher quality by proper treatment, which enables further reduction in nitride thickness and extension of scaling limit for the existing storage dielectric. A 164% leakage current improvement without sacrificing the cell capacitance can be achieved through this process, while keeping the outstanding reliability performance of less than 438 ppm failure rate after a ten-year operation. Most importantly, this new process can be fully integrated into incumbent furnace process, which means that no additional tool investment is required, and it is crucial for trench DRAM manufacturers to maintain their competitive advantage before the high-k material prevails at 65 nm technology node.     

Understanding the effects of wave function penetration on theinversion layer capacitance of NMOSFETs

A comprehensive analysis of the effects of wave function penetration on the capacitance of NMOS capacitors has been performed for the first time, using a self-consistent Schrodinger-Poisson solver. The study reveals that accounting for wave function penetration into the gate dielectric causes carrier profile to be shifted closer to the gate dielectric reducing the electrical oxide thickness. This shift increases with increasing gate voltage. For example, in one simulation, the peak is shifted by about 0.2 nm at a surface field of 1.96 MV/cm and 0.33 nm at a surface field of 3.7 MV/cm. This shifting results in all increased capacitance. The increase in capacitance observed in the inversion region is relatively insignificant when a poly gate electrode with a doping of less than 1×10²⁰ cm^-3 is used due to the poly-depletion effect. A physical picture of the effect of physical thickness on the tunneling current is also presented