Test structures to measure the Seebeck coefficient of CMOS ICpolysilicon

We report on two thermal characterization structures to measure the Seebeck coefficient α of CMOS IC polysilicon thin films relevant for integrated thermal microtransducers. The test structures were fabricated using a commercial 1.2 μm CMOS process of Austria Mikro Systeme (AMS). The fabrication of the first structure relies on silicon micromachining. In contrast the second, planar, structure is ready for measurement after IC fabrication. The temperature dependent α of the two polysilicon layers of the AMS process was measured with both devices. The agreement between the thermoelectric coefficients obtained with the two types of structures is better than 2.1 μV at 300 K     

Test chip based approach to automated diagnosis of CMOS yieldproblems

The authors describe a design approach for, and experimental results obtained from, a test chip developed for the purpose of automated diagnosis of random-defect-dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Test structure selection, sizing, layout, testing, and data analysis are discussed, and examples of rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnosis are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are summarized     

Beating the heat [CMOS hot-carrier reliability]

CMOS hot-carrier reliability at both transistor and circuit levels has been examined. Accurate reliability assessment requires defining suitable criteria for acceptable performance for both circuit and individual transistors. As device designers meet demands for greater speed and more complex circuitry accompanied by shrinking the size of transistor into the deep-submicron regime, they have to contend with increase in current densities and higher electric fields. Though in general a MOSFET's driving capability increases as the channel length decreases, the resulting high field will eventually limit the driving capability of the device. The authors discuss improving CMOS hot-carrier reliability through analysis, modelling and simulation     

Synchronous-mode evaluation of delays in CMOS structures

The extension of the explicit formulation of delays in CMOS VLSI to synchronous-mode evaluation allows the accurate evaluation of data path timing (few percent with respect to SPICE simulation) of general CMOS structures for all available input drive configurations, resulting in fast identification of timing problems. A validation of this method has been done using general series parallel networks. It was shown to be sufficiently accurate for resolving race problems. An implementation of the proposed algorithms has been conceived as a preprocessor for an event-driven switch simulator and it has been shown to be fast enough for use in VLSI timing analysis     

Design and evaluation of ion-implanted CMOS structures

An IC chip intended for the integrated signal readout of PbS-Si heterojunction detectors has been designed using a p-well/ n-substrate CMOS structure, The chip contains integrated and discrete n-MOSFET readout circuits as well as test structures. The chip fabrication used ion implantation for all doping steps, including the p well. The fabricated device profiles show good agreement with the results of a process analysis performed using the SUPREM program. Among the experimental n-MOSFET characteristics measured were:g_{m} = 230µmho,mu_{ch} = 240cm²/V . s,V_{br} geq 200V, andN_{ss} = 1.26 times 10^{11}/ cm². eV.     

Fabrication of fully self-aligned joint-gate CMOS structures

A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and PMOS transistors have been characterized and together are functional in joint-gate CMOS inverters.     

CMOS存储器IDD频谱图形测试

通过对CMOS存储器IDD频谱图形测试过程的介绍,测试及试验数据证实CMOS存储器IDD频谱图形测试是可行的。     

The characteristics of CMOS devices in oxygen-implantedsilicon-on-insulator structures

The characteristics of CMOS devices fabricated in oxygen-implanted silicon-on-insulator (SOI) substrates with different oxygen doses are studied. The results show that transistor junction leakage currents are improved by orders of magnitude when the oxygen dose is decreased from 2.25×10¹⁸ cm^-2 to 1.4×10¹⁸ cm^-2 . The floating-body effect, i.e. transistor turn-on at lower gate voltage with dramatic improvement in subthreshold slope when the drain voltage is increased, is enhanced by the reduction in leakage current and hence the oxygen dose. In SOI substrates implanted with 1.4×10¹⁷ cm^-2 oxygen dose and annealed at 1150°C, back-channel mobilities are decreased by several orders of magnitude compared to the mobilities in the precipitate-free silicon film. These device characteristics are correlated with the microstructure at the silicon-buried-oxide interface, which is controlled by oxygen implantation and post-oxygen-implantation anneal     

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide–nitride-oxide–silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.     

一种CMOS微电子测试图形的设计

本文介绍一种CMOS集成电路微电子测试图形——E2-PED,它是针对CMOS EEPR-OM电路的研制而设计的,也可以用于一般的CMOS电路工艺:文章描述了E2-PED所含有的各种微电子测试结构以及设计布图,给出了这些结构的构成及其作用。     

Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.     

板式换热器换热能力测试方法研究

板式换热器可在冬季及过渡季节实现冷冻水的自然冷源利用,在数据中心广泛应用,但对于运维而言其实际的换热能力难以得到有效评估.本文结合实际运维经验,提出一套适用于现场板式换热器的性能测试及计算方法.该方法不受环境气候条件和IT负载大小的影响,具有很强的可操作性,从而解决了数据中心在建设与运维过程中普遍存在的性能测试难问题.     

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

Validation of yield models with CMOS/SOS test structures

A methodology assessed to implement wafer level reliability relies on the design of specific test structures which must be as similar as possible to functional circuits geometries and lay-outs. In a second step, electrical tests provide wafer level data to validate the use of the Poisson yield model which gives defect densities. It is found that chips from the central area of the wafer present randomly distributed defects whereas those from the periphery are governed by a more systematic distribution.     

New Test Structure to Monitor Contact-to-Poly Leakage in Sub-90 nm CMOS Technologies

The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of-the-art CMOS process technology.      

高热流密度热沉散热能力数值仿真分析

固体激光器增益介质的热效应问题严重制约了高功率固体激光器的发展。本文从实际应用角度出发,通过数值仿真实验对比散热热沉的主要几何参数(包括热沉基底厚度、肋片高度、肋片宽度、肋片间距)对散热效果的影响;同时也分析了不同的外部流量条件下热沉的散热性能。计算结果表明:优化热沉几何参数,选取适宜的流量,热沉散热效果会有一定提升。     

回路热管传热特性的测试与分析

回路热管(LHP)是一种利用工质蒸发和冷凝的相变传递热量的高效传热装置。为研究LHP的换热特性,制作了简单的LHP传热性能测试装置。LHP原材料采用不锈钢,工质为二次蒸馏水,毛细吸液芯为500目的铜丝网。实验研究了热负荷及倾斜角度对回路热管传热特性的影响,结果表明,LHP的启动时间和阻值随着加热功率的增加而降低,而随着倾斜角度的单调增大,LHP的启动时间和阻值则呈现先减小后增大的趋势,表现出优越的传热特性。研究结果为LHP在不同安装场合条件下的运用提供一定的实验依据,同时也为现代电子设备散热问题提供了的一种解决途径。     

热容模式下片状激光介质的热畸变

利用有限元数值方法,模拟计算了热容模式下片状激光介质的瞬态温度分布和热应力分布及其波前畸变和应力双折射。结果表明:激光介质中的温度分布和热应力分布与抽运光斑及介质的几何形状密切相关。当抽运光斑未充满激光介质时,介质的表面靠近边缘处会出现大的拉应力集中,并且介质中最大拉应力和表面的最大轴向位移随抽运光斑尺寸缩小而增大;而当抽运光充满介质时,表面是压应力,较小的拉应力存在于介质内部。介质变形和热光效应(折射率随温度变化)是产生波前畸变的主要原因。热应力双折射对光束产生较大的退偏作用,从而影响激光器的输出性能。     

Test Engineering for CMOS Gate Arrays with the CAD-System VENUS 1

This paper describes the application of the computer-aided design/computer-aided testing (CAD/CAT) system VENUS 1 at Siemens for testing CMOS gate arrays [1]. The requirements for and the industrial aspects of CMOS gate array testing will be discussed.     

Method of dissipating heat generated in high-voltage CMOS driver IC

A method of dissipating the heat generated in a high-voltage CMOS driver IC, which is designed for use with a flat panel display, is proposed. It utilises a charge pump circuit to reduce the voltage across the driver IC when its output stages change their status. It can reduce the power consumption and relieve the thermal problems of driver ICs.