Reliability of Complementary MOS Integrated Circuits

This paper describes the results of tests of the stability and reliability of complementary MOS (CMOS) integrated circuits (IC). Operating life-tests at 125°C indicated excellent stability of electrical characteristics of both n-channel and p-channel transistors. Over three million device-hours of accelerated operating life-tests indicated a calculated failure rate, at a 60-percent s-confidence level, of 0.08%/1000 hours at 125°C, which corresponds to 0.01%/1000 hours at 55°C or 0.003%/1000 hours at 25°C. Field-usage reliability data on three satellites in orbit indicate a total failure rate of 0.003%/1000 hours (over thirty-four million operating hours with no failures). The observed failure rates are compared with other available data on IC reliability, and it is concluded that the reliability of CMOS ICs is equal to that of p-channel MOS circuits or of bipolar digital circuits of equal complexity, when each type is prepared by a well-controlled process, and operated at the same temperature. The operating temperature of CMOS IC chips in electronic systems is, however, generally lower since logic functions are accomplished at lower dissipation per gate.     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

Silicon-gate technology

Silicon-gate technology provides an advantageous approach for implementing large-scale integrated arrays of field-effect transistors. Its advantages?principally resulting from the low threshold voltage and the self-aligned gate structure buried under an insulator?ease the problem of interfacing these circuits to bipolar integrated circuits and increase both their performance and functional density, making MOS integrated circuits easier and more economical to use. This article reviews recent progress with this technology and shows its application to the construction of complex digital functions as illustrated by a memory circuit.     

MOS-bipolar monolithic integrated circuit technology

A technique for the fabrication of p-channel MOS transistors and bipolar transistors within monolithic integrated circuits is described. Total process compatibility has been achieved without compromising either the n-p-n bipolar or p-channel MOS characteristics. The technology developed is similar to that used for conventional integrated circuits until the channel oxidation step, A low temperature oxidation followed by a high temperature anneal process that produces negligible changes in preceding diffusion profiles was used to form this oxide. Bias temperature tests of MOS capacitors have shown the oxide to be reproducibly free of contamination. A high slew rate MOS bipolar operational amplifier has been designed and fabricated on 0.045- by 0.045-in chip using the new technology. Typical characteristics are slew rate =80 V/µs voltage gain = 70 dB. The MOS transistors are used as active loads and level shifters in this circuit and provide a much improved frequency response over conventional circuits using p-n-p lateral transistors.     

Aluminum metallization—Advantages and limitations for integrated circuit applications

The advantages and limitations of aluminum metallization are reviewed and compared with other systems used for integrated circuits. Metallization system properties of particular importance are summarized, including initial physical and chemical properties of the system which define potential performance and reliability considerations. The special requirements for MOS arrays and for multilevel-metallized integrated circuits are described. Recently available knowledge of aluminum metallization process technology and of metallization-related failure mechanisms is reviewed, and new results of experimental studies are presented. It is concluded that aluminum will continue to be the most widely used metallization material, not only for single-level metallized integrated circuits, but also for multilevel LSI arrays.     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Design aspects of MOS-controlled thyristor elements: technology,simulation, and experimental results

2.5-kV thyristor devices have been fabricated with integrated MOS controlled n⁺-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 μm were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Experimental Evaluation of Reliability of Deep Submicron SOI MOS Transistors at High Temperatures

In this paper, 0.18–0.5 μm SOI MOS transistors are tested for compliance with the reliability criteria applied to high-temperature electronics and their components. The main parameters of SOI MOS transistors are measured in the temperature range from ?60 to +300°С. The specific behavior exhibited by SOI MOS transistors at high temperatures should be taken into account when designing high-temperature integrated circuits so as to avoid premature failures and increase the reliability of devices.     

Monolithic integration of 5 V CMOS and high-voltage devices

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are available in this technology, including bipolar transistors, lateral MOS gate power devices, and high-voltage p-channel power devices     

A method for the measurement of the turn-on condition in MOS transistors

Metal-oxide-silicon (MOS) integrated circuits usually consist of MOS transistors and interconnections. Both, interconnections and MOS transistors are built up of diffused regions in the bulk substrate and conductive strips (metal or polycrystalline silicon) on top of the oxide. For proper electrical operation the interconnection paths should not exhibit MOS transistor effects, i.e. should not induce inversion layers at the silicon-silicon dioxide interface. Furthermore from a designer's point of view it will be desired that some transistors operate in the saturated mode and others in the non-saturated mode. This implies that a method for the determination of the turn-on of channel conduction is highly desirable for designers of MOS integrated circuits. Using a straightforward definition of turn-on, a fast and simple measurement method will be presented for the determination of the relation between gate voltage and diffused region voltage for MOST structures in the turn-on condition.     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.     

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Experimental sync separator and associated circuitry in integrated form

An experimental integrated circuit that performs the functions of sync separation, noise inversion, and AGC amplification was designed and fabricated. The IC uses p-channel enhancement-type MOS units as active transistors, diodes, and resistors. The threshold voltages permit the design of voltage-regulator circuits for the reference levels in the various signal-processing stages. The results of a test of the IC in combination with a commercial TV receiver are described.     

Transient Analysis of Four-Phase MOS Switching Circuits

Four-phase MOS switching circuits lend themselves readily to utilization on large-scale integrated arrays and possess many attractive and practical features. A model for transient analysis is presented. The evaluation and analysis of a generalized four-phase MOS gate which can implement a complex logic function are discussed.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

The metal-nitride-oxide-silicon (MNOS) transistor—Characteristics and applications

Recent advances in silicon nitride deposition techniques have led to the emergence of the metal-nitride-oxide-silicon (MNOS) integrated circuit technology as an alternative and supplement to the existing MOS technology. Applications of MNOS field-effect transistors have been proposed for both logic circuits (as an alternative to MOS transistors) and nonvolatile memory arrays This paper reviews the characteristics and applications of MNOS transistors. It presents a unified approach to the characterization of both stable and variable turn-on voltage MNOS transistors. The analysis is based on an extensive investigation of charge transport and storage in MNOS structures. The different modes of transistor operation are described and analyzed in terms of the physical parameters of the two-layer dielectric structure. Understanding of the physical mechanisms underlying transistor operation is applied to the optimization of transistor structure and performance for different digital integrated circuit applications. The feasibility of these applications is demonstrated by fabrication of a nonvolatile semiconductor storage array and a nonvolatile flip-flop.     

Threshold voltage variations with temperature in MOS transistors

Variations with temperature in the threshold voltage of n- and p-channel MOS transistors are obtained by calculation as well as measurement, with the results comparing quite closely. The amount of voltage change per °C under normal operating conditions is found to be dependent upon the channel doping concentration. The calculations show that for either n- or p-channel devices the voltage change per °C is -4 mV/°C for an impurity concentration of 3 × 10¹⁶/cm³and -2 mV/°C for an impurity concentration of 10¹⁵/cm³. This information is important because if the MOS transistor is subjected to a changing temperature environment, the accompanying threshold voltage change may be intolerable.