集成运放制造技术的新进展

集成运算放大器是模拟集成电路（IC）最早发展的一个分支。需求的牵引和技术驱动是模拟IC技术发展的两个轮子。一方面卫星通信、红外制导、高保真音响、精密仪表等领域对半导体器件包括运算放大器的性能提出了更高的要求；另一方面工艺技术的进步也为进一步提高运算放大器的性能提供了保障。几十年来，运算放大器性能的提高王要表现在以下10个方面上：高增益；高输入阻抗；高精度；高速度；低功耗；低噪声；低漂移；高电压；宽频带；大功率。要将这10个方面性能提高集中于一个运算放大器里是非常困难的。原因是这10个方面的要求有的在设计…     

高性能集成运放的教学与应用

论述了高性能集成运放教学的必要性、必要的知识铺垫和主要知识点。列举了三种不同高性能运放的应用实例。     

如何区分运放的线性与非线性应用

本文通过对电压比较器中的集成运放工作区域的讨论,说明了在集成运放的应用电路中,如何区分运放的线性与非线性应用的方法,兼与有些教材的有关内容作一商榷。     

高性能模拟集成运放中的增益增强技术分析

本论文针对高性能模拟集成运算放大器设计中用于开环增益增强的各种技术,从理论和仿真实践两个方面进行分析,总结出各种增益增强技术的优缺点,为在高性能的模拟集成运算放大器设计中增强增益提供选择依据。     

单电容米勒补偿三级运放设计

为了满足低压电路的工作要求,我们设计了一种新型的三级运放.该运放采用单电容米勒补偿与交叉多径嵌套补偿结合的方法,利用前馈通路在左半平面形成的零点来补偿其在主通路中的极点.通过使用TSMC 0.18μm工艺仿真.仿真结果表明:该运放能够获得113 dB的增益.有着87°的相位裕度,在1.8 V电源电压和120 pF负债的情况下.整体功耗只有0.534 mW.由此可见,这种新型的补偿方式能够有效地对运放进行补偿,并且使运放获得较高的增益以及较大相位裕度.     

一种两级运放中消除右半平面零点的新结构

提出了一种新的两级运放结构,可以消除由密勒补偿电容引起的右半平面零点。该结构采用多路径零点取消(MZC)的理论,不同于传统的方式,该结构直接利用了第二级的负载管,来引入前馈通路取消右半平面零点,简化了电路,降低了功耗。     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

使用新款ADC构建高性能数据采集系统

本文分析了数据采集电路在工业控制系统中的作用，介绍了几款最新的16位ADC，用于构建高性能的数据采集系统。     

High-gain microwatt composite cascode op amps

This article discusses the composite cascode stage, both single-ended and differential, operating in the weak inversion or moderate inversion region. The gain of the MOS composite cascode differential stage can exceed 100,000?V/V, a figure that has never been reported in the literature. For low-frequency applications, this configuration can be used to fabricate op amps that have high-gain, low-power and low-nonlinear distortion. Two different architectures, both having two gain stages are reported. The first op amp uses the Widlar architecture to achieve a gain of 117?dB, a power dissipation of 110?µW and uses a compensation capacitor of only 3.5?pF. The second op amp uses a class AB stage for the second and final stage and utilises the parasitic capacitance at the output of the first stage for compensation. This self-compensating op amp has a gain of 110?dB and a power dissipation of 21?µW.     

Noise performance of the new Norton op amps

The noise performance of the new "Norton" single-ended operational amplifier is described in detail. The important noise sources are introduced theoretically, and it is shown that the absolute noise levels can be accurately predicted and simply modeled under any bias conditions. The results are verified experimentally, and an example of a bandpass active filter is used to illustrate the accuracy of the model.     

A low-voltage BiMOS op amp

Describes the development of a threshold implanted BiMOS amplifier IC optimized for 2-5 V operation at a supply current of 300 /spl mu/A. A nonlinear operational transconductance amplifier (OTA) buffer having on-chip feedback provides a low-impedance rail-to-rail output, and a bulk-modulated PMOS input pair extends the common-mode range. Protective-network bootstrapping makes possible subpicoampere input-bias currents below 85/spl deg/C, and improved offset stability is achieved by the choice of threshold-level stage currents. Amplifier design is straightforward and readily applied from `micropower' to `broad-band' operating ranges. The combination of these features has produced a unique high-performance integrated circuit.     

The response of 741 op amps to very short pulses

A 741 op amp behaves like a monostable multivibrator when very short pulses are applied to the noninverting input terminal. It is shown that perturbations on the power supply lines or at the output of the amplifier will directly or indirectly have the same effect on the op amp.     

A fourth-order bandpass delta-sigma modulator with reduced numbersof op amps

A switched-capacitor quadrature demodulation technique, which is insensitive to first-order errors resulting from 90° phase inaccuracy and path mismatch, is demonstrated to shift a band-pass spectrum directly to dc. A sampling rate of four times the passband center frequency facilitates the quadrature demodulation and removes the 90° phase error. Furthermore, the path-mismatch error is canceled using the same signal path repeatedly, thereby reducing the number of op amps. A fourth-order band-pass Δ-Σ modulator, integrated in an area of 1 mm² using 2-μm CMOS, consumes 0.8 mW with a single 3.3-V supply and exhibits an SNR of 56 dB within a 30-kHz bandwidth     

N-folded cascode technique for high frequency operation of lowvoltage op amps

A technique is described which enhances the high frequency operation of a low voltage folded cascode structure by introducing a zero at the nondominant pole position and providing phase compensation. This technique can be used to develop low voltage operational amplifiers with good gain bandwidth properties and no overhead in power consumption     

High performance op amps in a 40V BiCMOS process and their applications

This paper describes the design of three high-performance op amps in a 40V BiCMOS technology. The first circuit is a low-noise op amp with MOS inputs. A thermal noise level as low as with a 1/f noise corner frequency of 100 Hz is achieved. For applications that can tolerate a lower input impedance, a more economical bipolar input low-noise op amp has been designed, yielding an even better noise performance for source impedances up to 20 k. The third circuit is an internally compensated high-gain-bandwidth (GBW=15 MHz) op amp that can drive loads from 0 to 20 pF. A fourth-order low-pass switched-capacitor filter making use of the latter op amp is discussed next. Finally the applications of this 40V BiCMOS process are illustrated.     

Using the weak inversion region to optimize input stage design of CMOS op amps

Operation of MOS devices in the strong, moderate, and weak inversion regions is considered. The advantages of designing the input differential stage of a CMOS op amp to operate in the weak or moderate inversion region are presented. These advantages include higher voltage gain, less distortion, and ease of compensation. Specific design guidelines are presented to optimize amplifier performance. Simulations that demonstrate the expected improvements are given.     

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However, the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition, design guidelines are suggested and test results are presented.     

NexFET:一种高可靠与高性能的低压功率DMOSFET

本文介绍一种具有高性能和高可靠性的新型低压功率MOSFET——TI公司的NexFETTM,它将一种高可靠、高性能的RF LDMOSFET与齐纳二极管组合。基于MOSFET结构的RF LDMOSFET将品质因数(Ron*Qg)改善两倍。一个纵向集成的齐纳二极管钳制峰值开关节点电压的尖峰形成,从而使MOSFET免受击穿。