A polyimide-based capacitive humidity sensor

The design of a relative humidity sensor is studied in which the principle of operation is based on the change of dielectric constant of a thin film of polyimide. The design of the sensor is established in such a way that it would be suitable for an integrated-circuit type of fabrication. The studies have shown that the experimental data are described well by the use of the Looyenga equation for dielectric constant behavior coupled with the Dubinin equation to describe the absorption as a function of relative humidity.     

电容式湿度传感器的设计

为了能够更好解决测量流动蒸汽湿度准确度低、难度大等问题,设计了一种电容式湿度传感器,其为同轴圆筒式多极电容传感器结构,利用电容数字转换技术芯片PCap01进行电容值的检测,通过SPI通信方式将测量结果传输到STM32单片机中进行处理,采用AD421将输出结果转换为标准的4~20 m A信号。实验结果表明,在一定温度下,随着产生湿度的变化,湿度与输出电流呈线性关系,当产生的湿度不变时,电流趋于稳定状态,该设计能够进行湿度的测量。     

高分子电容型湿度传感器研制

随着工业的快速发展,对温度检测和控制日益严格,温度传感器已无法跟上人们的需求,通过优化湿度传感器的表面结构和对感湿材料微孔设计提高了感湿特性,增强感湿材料的感湿特性,并对湿度传感器测量电路进行改进,提高微小电容测量,设计湿度测试系统。通过实验验证了改进后的湿度传感器测量效果更优越。     

CMOS电容式湿度传感器特性研究

提出了一种CMOS电容式湿度传感器特性研究方案.研究所用的微电容湿度传感器由标准CMOS工艺结合MEMS 后处理技术加工而成.为了测试湿度传感器的响应时间,设计了一种响应时间测试装置.测试结果表明,该电容式湿度传感 器在相对湿度25％～95％的范围内具有较好的线性度;其回滞在75％RH时达到最大,为2％ RH;该传感器...     

CMOS工艺聚酰亚胺电容型湿度传感器的研究

以正胶光刻和干湿刻蚀方法,结合CMOS工艺制备了聚酰亚胺电容型湿度传感器.研究了硅基、钼-铝栅条状电极湿度传感器的结构及亚胺化温度对其性能的影响.结果表明:相对湿度(RH)为20%～80%发生准静态变化时,该传感器的湿度-电容曲线具有较好的线性度;外界相对湿度在12%和92%间发生阶跃变化时,响应时间约为40 s.     

A smart capacitive angle sensor

This paper presents a smart capacitive angle sensor suited for automotive and industrial use. To comply with tough constraints of such applications in terms of environmental conditions, unit costs, and physical size, a fully integrated solution is mandatory. However, the limitations and capabilities of a single mixed-signal integrated circuit have considerable impact not only on the hardware architecture of the digital and analog system components, but also on the feasible measurement algorithm. A thorough investigation of all major nonlinear effects leads to an accurate system-level model of the sensor which is used to design a robust and reliable fully integrated sensor system capable of handling signal offset and amplitude variations. In addition, the proposed system recognizes and reacts on electromagnetic disturbances. Measurements taken from a final prototype comply with the simulation results.     

A monolithic capacitive pressure sensor with pulse-period output

A new microminiature monolithic capacitive pressure transducer (CPT I) is 20 times more sensitive than piezoresistive strain-gauge pressure transducers, requires one percent of the power, and can be batch fabricated through current integrated circuit technology. A second device (CPT II) incorporates bipolar signal-processing electronics on the same silicon chip to produce a low-duty-cycle pulse-mode output with period related to pressure. This output format helps to re-solve the problem of shunting between leads, which is one of the principal causes of long-term drift in piezoresistive transducers designed for implantable medical applications. Because this device uses capacitance change as a transductional mechanism rather than piezo-resistivity, it is not susceptible to drift caused by temperature variations in the piezoresistive coefficient. Optimization for totally implantable biomedical applications places special emphasis on small size, high sensitivity, improved long-term baseline stability, and greatly reduced power consumption. These properties are also important for a wide range of pressure-sensing applications-from automotive to general industrial use.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

CCD image sensor with compensated reset operation

A low voltage charge coupled device (CCD) image sensor has been developed by adjusting the electron potential barrier in the electron sensing structure. A charge injection to the gate dielectrics of a MOS transistor was utilized to optimize the electron potential level in the output structure. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 V to 5.5 V, which is suitable for compensating the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole–Frenkel conduction and Fowler–Nordheim conduction. A CCD image sensor with 492(H) × 510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

A piezoresistive microcantilever magnetic-field sensor with on-chip self-calibration function integrated

A micromachined piezoresistive cantilever magnetometer, with a self-calibration function on-chip integrated is presented . When the cantilever is subjected to a magnetic field to be measured, the magnetic force will exert upon the magnetized nickel thin-film pattern that is located at the cantilever end. The magnetic force bends the micromechanical cantilever, which is further read out by an integrated piezoresistor. For realizing the self-calibration function, an aluminum spiral is integrated around the cantilever to provide an artificial magnetic field, when an electric current flows through the spiral coil. The artificial magnetic field can be used to drive the cantilever bending and causes a self-calibration output signal. With this on-chip self-calibration scheme, the detection of magnetic field can be immune to the long-term drift in remanence of the magnetized nickel pattern, thereby, improving the sensing stability. Bulk micromachining technologies are used to fabricate the sensors. The formed sensor is used for magnetic-field measurement, resulting in the piezoresistive sensitivity as 1.06×10⁻⁴/mT and the sensing resolution 4.58 μT.     

一种新型的CMOS集成湿度传感器

利用MEMS技术，对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造，采用梳状铝电极结构、梳状多晶硅加热结构，衬底接地，感湿介质采用聚酰亚胺，利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路，输出可测电压信号，利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系。     

一种新型的CMOS集成湿度传感器

利用MEMS技术 ,对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造 ,采用梳状铝电极结构、梳状多晶硅加热结构 ,衬底接地 ,感湿介质采用聚酰亚胺 ,利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路 ,输出可测电压信号 ,利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系     

A novel approach to high-speed high-resolution on-chip mass sensing

The state-of-the-art mass sensing so far has been rather developed along the resolution axis, reaching atomic-scale detection, than into the direction of high-speed. This paper reports a novel self-calibrating technique, making high-speed inertial mass sensors capable of instant high-resolution particle detection and weighing. The sensing nanoelectromechanical resonator is embedded into a phase-locked loop and the sensor-inherent nonlinear phase–frequency relation is exploited for auto-calibration. A tunable on-chip carbon nanotube based mass balance serves as a case study of small-size and low-cost environmental and healthcare applications. Tunability and a phase-locked loop topology make the system widely universal and invariant to nanotube characteristics. Operational for tube eigenfrequencies up to 385 MHz, the circuit integration in a 180 nm technology achieves instantaneous zeptogram resolution, while yoctogram precision is obtained within the tenth of a second. These figures of merit range at the physical limits of carbon nanotube resonators, in both mass- and time-resolution.     

A high-speed ultra-low power 64K CMOS EPROM with on-chip test functions

A 100 ns 8K /spl times/ 8 CMOS EPROM has been developed. Internal clock signals generated by address transition detection are used to reduce power consumption. As a result, power dissipation is less than 5 mW/MHz in the active mode, and less than 1 /spl mu/W in both the standby mode and the active quiescent mode (chip enabled, but no address transitions sensed). Three special test features incorporated in the design can be used to reduce the time required for final test and reliability screening.     

电容式湿度传感器性能测试方法分析

湿度传感器产品及湿度测量属于90年代兴起的行业。如何判断湿度传感器的性能，这对一般用户来讲，仍是一件较为复杂的技术问题。针对目前湿度传感器在生产过程中还停留在手工测试所存在的一些问题，对电容式湿度传感器进行了详细地分析，利用电容式湿度传感器的等效形式，阐述了使用复数电压法测量对湿度传感器的测量过程，建立了复数电压法电容式湿度传感器性能测试数学模型。     

Modeling, simulation and temperature compensation of porous polysilicon capacitive humidity sensor using ANN technique

The porous polysilicon capacitive sensor used for measuring relative humidity has the advantages of low cost, ease of fabrication and CMOS compatibility. However, the capacitance of the sensor, which is a function of concentration of water vapour, also depends on ambient temperature. Thus, variation of ambient temperature causes error in the performance of sensor outputs. In this paper, two ANN models have been developed. The first model is used to simulate the behavior of the capacitive humidity sensor (CHS). This model can also be used for on line monitoring of the fault of the sensor. The second model is based on inverse modeling, which can be used to compensate the effect of ambient temperature error. It is found from the simulation studies that the error of the direct model is within ±2% of full scale and for the inverse model the error is within ±0.5% of full scale over a temperature range from 20 to 70 °C. A hardware implementation scheme for realization of the CHS model is also proposed.     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.     

Low voltage CCD image sensor with optimized reset operation

A charge coupled device (CCD) image sensor operating with 3.0 V-reset has been developed using a charge injection to the gate dielectrics of a MOS structure. A DC bias generating circuit was added to the reset structure, which sets reference voltage and holds the signal charge to be detected. The generated Dc bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 to 5.5 V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with 492(H)×510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

A new touch mode capacitive pressure sensor with two deformable diaphragms

To achieve the characteristics of better linearity, a new type of touch mode capacitive pressure sensor named as DDTMCPS is devised, which has a pair of deformable sensing diaphragms. Compared to present touch mode capacitive pressure sensors, the new sensor is characterized by better linearity, and large linear operation range. Such a device also has high sensitivity, and other advantages of normal touch mode capacitive pressure sensor. In the case of such a novel sensor, the second diaphragm served as bottom electrode plays great roles in modifying the deflection of the first diaphragm served as top electrode, furthermore optimizing the performance of touch mode sensors. Silicon fusion bonding technology is advised to fabricate the novel device.