Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.     

Investigations of solution variables in a contactless copper electrodeposition process for 3D packaging applications

A novel electrochemical method for contactless electrodeposition of copper onto silicon wafers has been investigated. Deposition parameters such as applied current, concentrations of deposition solution and supporting electrolyte were optimized to achieve high deposition rates as well as homogenous deposition of copper. Copper sulfate solution temperature of about 65 °C was shown to be suitable for achieving stable and high values of current density that translated to copper deposition rates of~2.4 µm/min with good deposition uniformity.     

三维集成电路中TSV-TSV的耦合分析与优化

TSV-TSV耦合会对三维集成电路的性能造成影响,主要的负面效应就是引入了耦合噪声。为了能够在初期设计阶段准确的估计TSV间的耦合强度,本文首先提出了存在于TSV间的基于二端口网络的阻抗级耦合通道模型,然后推导出了TSV间的耦合强度公式用来描述TSV-TSV耦合效应。通过与三维全波仿真结果的对比,公式的准确度得到了验证。另外,本文提出了一种减小TSV间耦合强度的设计方法。通过SPICE仿真,所提出设计方法不仅可以应用在简单TSV-TSV的电路结构中,还可以应用在含有多个TSV的复杂电路结构中,从而体现了所提出设计方法的可行性,并且为设计者提供了改善三维集成电路电学性能的可能性。     

Improving power analysis attack resistance using intrinsic noise in 3D ICs

Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic 3D models, this work demonstrates the impact of noise in PDN on the 3D chip's resilience against correlation power analysis (CPA) attack, which is one of SCA attacks. The characteristic of PDN noise is extracted from our experiments. To expand the natural defense originated from the 3D integration, this work proposes to exploit the PDN noise inherently existing in 3D chips to thwart CPA attacks. Instead of introducing external noise or flattening the power profile, the proposed method utilizes the spatially and temporally varied supply voltages from other 3D planes to blur the power correlation of the crypto unit. Both theoretical analysis and experimental validation prove that the proposed method can effectively enhance the resilience of a crypto unit embedded in the 3D chip against CPA attacks. Simulation results show the proposed method improves the average guessing entropy by 9× over the baseline. Emulation on an FPGA platform demonstrates that the proposed method successfully slows down the key retrieval speed of CPA attack, with significantly less power overhead than representable power equalization techniques. Test vector leakage assessment (TVLA) shows that the proposed method improves the confidence to accept null hypothesis 201× over the baseline.     

科学级CCD三维噪声模型及其评估

为了评估科学CCD噪声带给激光近场分布测量的影响,采用三维噪声模型,分析了科学级CCD的噪声,并将CCD的噪声分解为空间噪声和时间噪声。空间噪声用来评估CCD像元之间响应不一致性对测量的影响,时间噪声用来评估多次测量不一致性对测量的影响。通过设计测量系统对CCD三维噪声进行测量,并分析时空噪声的统计分布规律,发现两者均是依赖于信号、近似服从正态分布,建立了依赖于信号的时空噪声的数学模型,并实验验证了该模型是有效的。     

The effect of forming gas anneal on the oxygen content in bonded copper layer

Using a combination of copper (Cu) thermocompression bonding and silicon wafer thinning, a face-to-face silicon bi-layer layer stack is fabricated. The oxygen content in the bonded Cu layer is analyzed using secondary ion mass spectrometry (SIMS). Copper-covered wafers that are exposed to the air for 12 h and 12 days prior to bonding exhibit 0.08 at.% and 2.96 at.% of oxygen, respectively. However, prebonding forming gas anneal at 150°C for 15 min on 12-day-old Cu wafers successfully reduces the oxygen content in the bonded Cu layer to 0.52 at.%.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.     

Thermal characteristic of Cu-Cu bonding layer in 3-D integrated circuits stack

Copper (Cu) thermo-compression bonding of wafers can be used to fabricate multi-layer three-dimensional (3-D) integrated circuits (ICs). This work examines the thermal characteristic of the Cu bonding layer and demonstrates experimentally that Cu bonding layer can act as a spreading layer that helps in heat dissipation of bonded 3-D ICs stack more efficiently compared to silicon dioxide bonding layer. The use of Cu bonding layer in a double-layer stack of ICs provides better cooling by as much as 9 °C compared to oxide bonding interface.     

Linearization technique using bipolar transistor at 5 GHz low noise amplifier

A CMOS low noise amplifier (LNA) used in wireless communication systems, such as WLAN and CDMA, must have low noise figure, high linearity, and sufficient gain. Several techniques have been proposed to improve the linearity of CMOS LNA circuits. The proposed low noise amplifier achieves high third-order input intercept point (IIP3) using multi-gated configuration technique, by using two transistors, the first is the main CMOS transistor, and the second is bipolar transistor in TSMC 0.18 m technology. Bipolar transistor is used to cancel the third-order component from MOS transistor to fulfill high linearity operation. This work is designed and fabricated in TSMC 0.18 m CMOS process. At 5 GHz, the proposed LNA achieves a measurement results as 16 dBm of IIP3, 10.5 dB of gain, 2.1 dB of noise figure, and 8 mW of power consumption.     

谐振式硅基集成光学陀螺的偏振噪声建模与分析

偏振噪声是谐振式集成光学陀螺的主要光学噪声源,其存在大大降低了系统的精度,为了定量化研究谐振式集成光学陀螺偏振噪声的产生机理,利用琼斯矩阵和光束传播法建立了谐振式硅基集成光学陀螺偏振噪声模型,该模型综合考虑了波导传输介质中的光偏振态交叉耦合、应力双折射等的影响,有效地逼近了实际的物理系统。基于上述模型得出了谐振腔内二氧化硅波导本征偏振态交扰与陀螺极限输出之间的表达式。对波导谐振腔内与偏振相关的3个因素:输入光偏振态、温度波动和波导保偏性能进行了仿真分析。并通过在输入端插入高偏振度起偏器的实验装置,有效验证了所建偏振理论模型受输入光偏振态波动影响的正确性。     

像增强型CCD的噪声抑制和性能评价

为了有效降低像增强型CCD(ICCD)的噪声,提高系统信噪比并实现对图像噪声的评估.引入三维噪声数学模型,将ICCD输出数帧图像噪声按时间域和空间域划分为7项噪声.基于积分球光源系统建立了三维噪声测量系统,结合数字图像处理技术,经过试验统计和分析采用多帧积累设定波动阈值的办法有效地抑制了紫外成像仪关键器件ICCD的图像噪声,使图像噪声降低30%,信噪比提高57.6%.并应用三维噪声分析方法对噪声抑制前后的效果实现客观评价.三维噪声分析表明,该方法有效地降低了由于ICCD各种随机噪声而带来的时间域噪声,提高了ICCD输出图像的信噪比,同时也证明三维噪声分析法为评价微光成像器件的图像质量提供了一种可行方法.     

Modeling and design of 3-D MPPT for ultra low power RF energy harvesters

Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthermore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting.     

往复冲击条件下磨痕三维形貌的测量

提出一种采用傅里叶变换轮廓术(FTP,fourier transform profilometry)对磨痕三维形貌进行测量的方法,具有只需采集一帧条纹图、数据处理少、简单易行和测量速度快等优点,适于自动化测量。采用一种新的产生正弦光强方法,将正弦光强投影到试件表面产生包含三维形貌信息的光栅条纹,利用FTP重建磨痕的三维形貌。实验对不加润滑油状态下往复105次冲击后的磨痕形貌进行测量,并将实验结果与四步相移所测结果进行对比,验证了本文方法用于测量往复冲击条件下磨痕形貌的可行性,并为进一步研究往复冲击时接触润滑效应提供了新的实验依据。     

An investigation into warpages,stresses and keep-out zone in 3D through-silicon-via DRAM packages

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different.     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

Scaling potential of pin-type 3-D SBT ferroelectric capacitors integrated in 0.18 μm CMOS technology

In this work, the difficult scaling of FeRAM is circumvented by fabricating 3-dimensional ferroelectric capacitors stacked on W plugs and successfully integrated in 0.18 μm technology using MOCVD SBT. The effective remnant polarization was increased by 70% due to the sidewall contribution. Also, high reliability of 3-D capacitors was assessed. The samples showed no fatigue degradation after 10¹³ ±5 V cycles. From extrapolation of both imprint and retention results, a wide sensing window is kept after 10 years in most severe temperature condition, that is at 150 °C. Critical integration issues are discussed for further scaling in 0.13 μm technology and below.     

仓储场景中基于无线标签的三维定位方法

仓储行业在面向智能化发展中面临因无法获取物资的室内位置信息而导致出库、入库难等问题,为实现对物资准确定位,该文提出一种基于无线标签的目标3维定位方法。设计的无线标签安置在待定位物资上,将来自发射机正交频分复用(OFDM)信号反射到具有均匀面阵(UPA)天线阵列的接收机,进行多通道的信道估计后,利用分步的稀疏恢复算法实现高维无线信道参数估计,并结合发射机、标签和接收机的空间几何位置,建立标签位置的优化问题,最后采用群智能算法搜索得到目标准确的3维位置。为验证系统,实现了标签及收发机原型,实测结果表明,目标的中值3维定位精度达到0.53 m。