An asymmetrically doped buried-layer (ADB) structure forlow-voltage mixed analog-digital CMOS LSI's

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration “pocket” layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-μm channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region     

A novel high performance SiGe channel heterostructure dynamicthreshold pMOSFET (HDTMOS)

In this letter, we propose a novel SiGe channel heterostructure dynamic threshold metal oxide semiconductor (DTMOS) and demonstrate its superiority over conventional Si-DTMOS. The introduction of a SiGe layer for the channel is very effective for reducing the threshold voltage in spite of keeping impurity doping level at the body region. Therefore, a low threshold voltage and a large body effect factor can be achieved simultaneously. The SiGe HDTMOS with highly doped body exhibits two times higher transconductance, 1.4 times higher saturation current, and better short channel immunity than that of the control Si-DTMOS with lightly doped body of which threshold voltage is nearly the same     

Current gain of narrow-base transistors

It is shown that the total number of impurities per cm² in the quasi-neutral base region of narrow-base transistors and their current-gain β strongly depend upon the emitter-base voltage V_BE. The computed results demonstrate that the β of these transistors falls considerably with V_BE increase, even in the absence of high-injection effects. The analysis also shows that the collector current of narrow-base transistors increases slower than exp (V_BE/V_T) giving rise to a non-ideality factor greater than one. It is concluded that narrow-base transistors with higher base resistivities are more susceptible to these effects.     

Effects of the diffused impurity profile on the DC characteristics of VMOS and DMOS devices

Double-diffused MOS (DMOS) and V-groove MOS (VMOS) transistors have been simultaneously fabricated in order to investigate the effects of impurity profiles on device performance. Processing parameters are varied to achieve a range of channel lengths and peak channel dopings. The resulting impurity profiles are measured by the two point probe spreading resistance method. Properties of the lateral DMOS impurity profile are inferred from a comparison of the electrical characteristics of the VMOS and DMOS devices. It is found that conventional models inadequately simulate the output conductance of the devices in saturation. An expression for channel length modulation is derived from a one-dimensional solution of Poisson's equation in the region surrounding the channel-drain junction. When measured impurity profile data are incorporated into the new channel length modulation model, the output conductance of the devices is accurately simulated for channel lengths ranging from 0.6 to 2.0 /spl mu/m.     

A Mössbauer study of Fe impurity atoms in gallium arsenide

Mössbauer emission spectroscopy of the ⁵⁷Co(^57mFe) isotope was used to find the dependence of the charge state of Fe impurity atoms in GaAs on the Fermi level position in the band gap. Neutral and ionized states of impurity atoms both in the surface region (where impurity atoms form associations with lattice vacancies) and in the bulk region (where an impurity exists in the form of isolated substitutional atoms) are identified. In the bulk region of partially compensated samples, fast electron exchange between neutral and ionized acceptor Fe centers performed by holes via the valence band is revealed.     

Conductance of MOS transistors in saturation

The output conductance of MOS transistors operating in the saturation region is studied theoretically and experimentally. A simple physical model is described which accounts for the modification of the electric field in the drain depletion region near the Si-SiO2interface, due to the presence of the gate electrode. The saturation conductance is shown on the basis of this model to be a sensitive function of the oxide thickness as well as the substrate impurity concentration. Good agreement is obtained between theory and experiment over a wide range of device parameters. The characteristics of lowly doped very-short-channel devices, which depart from this theory, are also discussed. The departure is shown to be due to a "punch-through"-type phenomenon.     

Design and characterization of a step-recovery switching transistor

Fast rise time pulses can be generated with a special high-frequency silicon transistor structure having a collector impurity profile designed to control charge storage in the collector. When switched out of saturation it operates in a manner analogous to a step-recovery diode. The theory of operation is discussed along with the design and fabrication of the diffused impurity profiles. Its unique geometry combines planar and mesa technologies. Experimental transistors have a storage time of approximately 2-30 ns followed by a fall time as fast as 0.5 ns. The storage time can be adjusted by varying the initial base current or the driving pulse. The storage time and fall time are accurately characterized by the charge-control model. A transformer input circuit gives the best switching performance. Control devices of conventional planar structure fail to produce fast switching times. They demonstrate the failure of the charge-control model in describing the fall time of planar transistors in general.     

掺氮4H-SiC电子输运特性的多粒子蒙特卡罗研究

在最新能带结构计算的基础之上,采用非抛物性能带模型对掺氮4H-SiC电子输运特性进行了多粒子蒙特卡罗(Ensemble Monte Carlo)研究.研究表明,低场下,掺杂浓度较低时,氮杂质不完全电离导致的中性杂质散射对4H-SiC横向电子迁移率影响较小.随着掺杂浓度的增加,中性杂质散射作用增强.掺杂浓度较高时,随着温度的增加,中性杂质散射的影响逐步减弱.4H-SiC电子迁移率较高且各向异性较小,温度为296K时得到的横向电子饱和漂移速度为2.18×10⁷cm/s;阶跃电场强度为1000KV/cm时,横向瞬态速度峰值接近3.3×10⁷cm/s,反应时间仅为百分之几皮秒量级.模拟结果同已有的测试结果较为一致.     

Switching response of graded-base PN junction diodes

This paper extends the earlier analysis by Kingston of the switching response of a uniform-base diode to a graded-base diode. It concerns the time required to switch a diode from a forward-biased to a reverse-biased condition. The current transient can be separated into two phases: 1) the constant current phase during which the carrier density at the junction changes gradually from a forward-biased to a reverse-biased condition, and 2) the nonconstant current phase during which the injected carriers stored in the base region gradually disappear. In the present analysis, it is found that in a graded-base diode where the impurity concentration decreases from the emitter junction towards the base contact, the time for the constant current phase is greatly shortened because of favorable initial carrier distribution. The effect is already significant if the impurity concentration changes by a factor from 3 to 1 from the emitter junction to the base contact. To shorten the nonconstant current phase, however, a much larger change of impurity concentration, say of the order from 500 to 1, from the emitter junction to the base contact is needed.     

A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors

High-voltage double diffused metal-oxide semiconductor transistors (DMOST's) have been fabricated with drain-source breakdown voltage greater than 200 V. This paper describes an experimental and theoretical study of the current-voltage behavior of these devices leading to a two-component MOS field effect transistor (MOSFET)-resistor model appropriate for computer-aided circuit design. The effects of velocity saturation, mobility reduction, and nonuniform impurity concentration in the channel, and of spreading resistance in the drift region are considered. Parameter extraction for experimentally characterizing these effects is described. Comparison of experimental and theoretical results shows that the model accurately predicts the device I/V characteristics. The range of validity of the model is limited primarily by high current saturation effects.     

Photoeffect on diffused P-N junctions with integral field gradients

A detailed analysis of a diffused junction photodiode is presented in which the illumination, monochromatic or broad-band, is applied to the diffused face. The electric field produced by the impurity distribution, assumed exponential, assists the transport and collection of minority carriers created by photons absorbed in the graded region. The theoretical study covers both the steady-state and the transient response, and takes into account the effect of surface recombination velocity. The presence of the built-in field increases the photocurrent and reduces the dark current compared with homogeneous base diodes. For p-n silicon photodiodes with 5-micron base widths and acceptor concentrations of say, 2 × 10¹⁸atoms/cm³at the surface, photosensitivities of approaching 0.01 ampere per lumen may be achieved. The transient-response analysis considers the extrinsic delay imposed by the time constant of the junction capacitance and the load resistance, and also the inherent delay caused by the transit time of the minority carriers. With moderate or high load resistances, the extrinsic delay is much larger than the transit-time delay. However, for comparable graded- and homogeneous-base photodiodes, the capacitances of graded junctions are lower, and therefore the transient response is improved on this account. The graded junctions also are shown to have greatly reduced transit-time delays because of the built-in field effect.     

Optically controlled characteristics in an ion-implanted silicon MESFET

OPFETs (optical FETs) are useful as compatible IC transducers in optical communication systems, although APDs (avalanche photo diodes) have higher multiplication gain and speed of response. Studies have been made on the optically controlled characteristics of an ion-implanted Si MESFET which show that drain-source current can be enhanced with increasing radiation flux intensity and lower wavelength of operation. Furthermore, the threshold voltage is found to be reduced under normally OFF conditions and increased under normally ON conditions for higher flux density and lower wavelength. The effect of radiation becomes predominant over the impurity concentration at flux densities greater than or equal to 10¹⁸/m² and wavelengths less than or equal to 0.78 μm.     

活性制备聚合物分散液晶显示器件

合成了一种活性大分子试剂,将其引入聚合诱导分相法中,研究了其含量和光引发剂含量对PDLC光电性能的影响.结果表明:随着活性大分子试剂和光引发剂含量的上升,PDLC的关态透光率明显下降,阈值电压及饱和电压有所上升.文章对活性大分子试剂在聚合过程中的作用机理进行了分析.     

强激光近场分布测量中科学级CCD 的非均匀性校正

首先分析了引起CCD 非均匀性的原因,将其归纳为两个方面,一为因制作工艺、材料、偏置等因素引起的空间噪声,二为CCD 响应特性随时间的漂移而引起的时间噪声,两者的共同作用将严重影响CCD 的测量性能。为了能够定量描述空间噪声和时间噪声对CCD 产生非均匀性的影响,文中基于CCD 光电响应曲线呈线性状态这一假设建立了CCD 光电响应的数学模型,然后在该模型的基础上提出了利用最小二乘法来估计校正系数,从而消除CCD 的非均匀性,实验证明该算法是有效的。     

功率MOSFET零温度系数点的研究

为研究功率MOSFET零温度系数点（Zero Temperature Coefficient,ZTC）,不同栅极电压对温度系数的影响,本文基于阈值电压和迁移率的温度关系并结合功率MOSFET输出特性模型,得到了随栅极电压变化而出现的三种不同温度系数。利用实际测试验证了温度系数的变化规律,结果表明：在小栅极电压条件下,线性区和饱和区均为正温度系数;随栅极电压增大,线性区先进入负温度系数,饱和区仍然为正温度系数,并因此产生了零温度系数点;随栅极电压进一步增大,线性区和饱和区都进入负温度系数。同时根据测试数据,分析了ZTC在不同栅极电压条件下随温度的变化原因,并基于测试数据讨论了迁移率随栅极电压和温度的变化关系。     

Degradation of the parameters of transistor temperature sensors under the effect of ionizing radiation

The influence of the effective concentration of an impurity specifying the conduction type of the base region and the base thickness on the radiation resistance of transistor temperature sensors is investigated. The dependences of the forward voltage drop at the emitter transistor junction and current amplification factor on the magnitude of electron, neutron, and γ-quanta flows are revealed. It is found that degradation of the forward voltage drop under the effect of ionizing radiation begins at doses higher by almost two orders of magnitude than the current amplification factor depending on the transistor’s design features. The reproducibility of the temperature-sensitive parameter, which increases the yield percentage of suitable devices, increases after annealing of the electron-irradiated structures.     

Device characteristics of long-wavelength lasers based on self-organized quantum dots

The current state of the field of semiconductor lasers operating in the spectral range near 1.3 ??m and with an active region represented by an array of self-organized quantum dots is reviewed. The threshold and temperature characteristics of such lasers are considered; the problems of overcoming the gain saturation and of an increase in both the differential efficiency and emitted power are discussed. Data on the response speed under conditions of direct modulation and on the characteristics of lasers operating with mode synchronization are generalized. Nonlinear gain saturation, the factor of spectral line broadening, and the formation of broad gain and lasing spectra are discussed.     

A silicon symmetrical transistor utilizing an epitaxially grown base region

A silicon symmetrical transistor having high symmetry of current gains, extremely low saturation resistance and high-frequency performance is fabricated by utilizing ap-type wafer with extremely low resistivity for the collector, ann-type epitaxial layer grown on the wafer for the base and ap-type region diffused into the layer for the emitter of the transistor. High injection efficiencies of the two junctions are obtained owing to the high surface concentration of the emitter and the high impurity concentration of the wafer. A thin base of about 2µ in thickness, large junction areas of about 0.70 mm in diameter and the junction area ratio of about 0.9966, are used for high survival factors. The collector junction is formed in the epitaxial layer intentionally away from the interface, in order to have a nearly equal impurity distribution to that near the emitter, and to keep away from the crystal imperfections near the interface. Combination of diffusion-epitaxial technique with the optimum geometry results in the structure capable of replacing a number of other devices designed for specific functions. Good symmetry of current gains is obtained: the hFE's above 20 in the two directions at 10 µa to above 50 ma of collector currents. The saturation resistance is in the neighborhood of 1 Ω. Current gain band-width fTis greater than 20 Mc.     

大视场空间相机CCD 性能测试及筛选方法

空间相机使用CCD 拼接技术组成长焦平面,可有效地增加空间相机的视场和幅宽。拼接 CCD 之间的性能差异会影响空间相机的成像质量,为了在大视场空间相机研制时挑选高性能且性能一致的CCD,提出了一种大视场空间相机CCD 性能测试与筛选方法。首先,介绍了CCD 的成像电路设计、以及CCD 光谱特性和辐射特性的测试方法。然后,介绍了CCD 的筛选流程,第一步是从各 CCD 裸片的几何特性、信噪比、相对光谱响应、响应非均匀性、非线性、暗电流以及动态范围等角度进行筛选,将不满足指标的CCD 剔除,第二步是依据辐射响应一致性筛选出满足要求的CCD,通过数据分析比较得出饱和辐照度筛选法优于响应度筛选法。最后,采用饱和辐照度筛选法从10 片CCD 中筛选出饱和辐照度一致性最好的4 片CCD,饱和辐照度相对偏差为0.23%,该组CCD 已经被应用于某大视场空间相机的研制,并获得了良好的效果。     

Silicon variable capacitance diodes with high voltage sensitivity by low temperature epitaxial growth

Low temperature epitaxial vapor growth of silicon has been successfully applied to the fabrication of variable capacitance diodes which have a hyperabrupt impurity distribution profile. These diodes exhibit a strong nonlinear behavior in capacitance voltage characteristics; for example, one of the diodes has the value of n as high as 15 in the differential capacitance formula:dC/C = -n dV/(V + Phi). It has been found that the capacitance voltage and current voltage characteristics agree well with those calculated from the impurity profile so that the diodes with a high voltage sensitivity and with a high quality factor can be designed and fabricated reproducibly by this technique, and used in all solid-state FM modulators and automatic gain control units in a microwave relay system transmitting multiplex telephone signals. The double breakdown phenomenon in the current voltage characteristic of some diodes was observed and proved to be the saturation effect of generation recombination currents.