An architecture for real-time multimedia communication systems

A multimedia communication system includes both the communication protocols used to transport the real-time data and the distributed computing system (DCS) within which any applications using the protocols must execute. The architecture presented attempts to integrate these communications protocols with the DCS in a smooth fashion in order to ease the writing of multimedia applications. Two issues are identified as being essential to the success of this integration: the synchronization of related real-time data streams, and the management of heterogeneous multimedia hardware. The synchronization problem is tackled by defining explicit synchronization properties at the presentation level and by providing control and synchronization operations within the DCS which operate in terms of these properties. The heterogeneity problems are addressed by separating the data transport semantics (protocols themselves) from the control semantics (protocol interfaces)     

An architecture and compiler for scalable on-chip communication

A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-/spl mu/m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.     

Output-buffer switch architecture for asynchronous transfer mode

This paper proposes a new asynchronous transfer mode (ATM) switch architecture for the broadband ISDN. The ATOM switch ATM output-buffer modular switch has a multi-stage network structure, and is highly modular to facilitate capacity expansion. The ATOM switch element is of the output-buffer type with a time-division multiplexed bus and FIFO buffer for each outgoing line. Bit-slice techniques are used to implement the high-speed time-division bus and buffer memories. The output buffer switch has the advantages of no throughput degradation since internal contention is eliminated, and a simple control structure for providing priority and multi-point connections. This paper also deals with switching delay and buffer overflow probabilities for mixed (bursty and non-bursty) traffic.     

An hierarchical VLSI neural network architecture

As neural network systems are scaled up in size it will become extremely difficult, if not impossible, to maintain full connectivity. A digital architecture which exhibits hierarchical connectivity similar to that observed in many biological neural networks is described. At the lowest level, clusters of fully connected neurons correspond to subnetworks. These subnetworks are then sparsely connected to form the complete neural network system. The architecture exploits the inherent density and large bandwidth of on-chip RAM and can use either a large number of bit-serial processors or a reduced number of bit-parallel processors. A prototype chip which implements a complete subnetwork has been fabricated in 3-μm CMOS and is fully functional     

An analog neural computer with modular architecture for real-timedynamic computations

A multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable is described. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2-μm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications was tested successfully. Results of a network for real-time decomposition of acoustical patterns are discussed     

An enhanced and energy efficient communication architecture for Bluetooth wireless PANs

Bluetooth is a radio technology for Wireless Personal Area Networking (WPAN) operating in the 2.4 GHz ISM frequency band, and allows devices to be connected into short-range ad hoc networks. The Bluetooth medium access control protocol is based on the Master/Slave paradigm wherein any communication between slave devices has to go through the Master. While this model provides for simplicity, it incurs a longer delay between any two slave devices due to far from optimal packet forwarding, the use of double the bandwidth, and also additional energy wastage at the Master. Moreover, if more than two devices want to communicate as a group, this can only be achieved by either multiple unicast transmissions or a piconet-wide broadcast, clearly resulting in inefficiency. In this paper, we propose a novel Dynamic Slot Assignment (DSA) scheme whereby the Master device dynamically assigns slots to Slaves so as to allow them to communicate directly with each other without any Master intervention. This proposed communication architecture also provides for Quality of Service (QoS) requests, admission control, and multi-device conversation by which a multicast-like communication is implemented within a piconet. Through extensive simulation, we observe that DSA drastically enhances Bluetooth performance in terms of delay and throughput, while significantly reducing power consumption at the master and the overall piconet.     

An ALF communication architecture: design and automatedimplementation

The application level framing (ALF) principle states that information should be packetized by the application into application data units (ADUs), each of which should be at the same time a unit of transmission, a unit of control, and a unit of processing. This paper describes a communication system architecture based on the ALF principle, which then attempts to maximize what might be gained from using ADUs. In this architecture, protocols are tailored to application requirements, i.e., to ADU types. In a first approximation, we consider three specific requirements, namely, in-order delivery, reliable delivery, and real-time delivery. ALF-based systems promise performance gains; however, implementing them in practice might be a complex task. Therefore, we have developed a compiler that automatically generates ALF-based communication systems starting from formal specification of applications. We have used this compiler to generate protocols tailored to three specific applications. Experimental results show that the gains are linked to application “complexity”     

异步可重构结构设计

介绍一种异步可重构结构，研究了异步可重构单元的设计。通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明，异步可重构结构具有低功耗、高性能的优点，适合作为IP集成到系统芯片上，组成低功耗、高性能的可重构计算平台。     

MPEG-4多媒体移动通信系统的一种有效复用结构

介绍了一种基于MPEG－4标准的移动多媒体的两层复用结构。第一层对有相似服务质量（QoS）要求的基本数据流进行打包，形成具有较少QoS要求的数据流；第二层为每个数据流提供相应的防误码措施，形成可在易误码链路进行传输的单一数据流，达到既满足各个基本数据流防误码的要求,又使复用开销最小。     

An open architecture for digital communication systems.2. Creatingenabling standards for a digital communication infrastructure

The article addresses nine critical issues related to standards for an open architecture digital communications system. It proposes several specific concepts to illustrate how open architecture standards can be constructed. However, these concepts should be interpreted as examples, rather than specific recommendations. The issues are: image parameters; common raster representations; spatial resolution families; extensible representations; safe aperture; time based media files; local composition and navigation; temporal rate families; and modular standards     

异步光分组交换网的流量建模

研究了异步光分组交换网的流量特性，提出了网络流量的解析模型和近似模型。研究表明，在采用计时门限光分组组装算法的情况下，如输入IP流具有短程相关特性(ShortRangeDependent)，则光分组的到达间隔时间呈负指数分布，光分组的长度趋于高斯分布。     

A communication architecture for spontaneous systems

In this article a communication architecture concept for spontaneous systems is provided. The concept integrates application-level spontaneous group communication and ad hoc networking together. A service gateway is applied as a key architecture element to connect multiple technologies and networks together. A set of methods to enable plug and play, addressing and mobility, peer-to-peer connectivity, and use of services is provided. Finally, the provided methods are discussed based on the realized research experiments.     

Hypercube-based architecture for high speed communication systems

An implementation is presented of digital demultiplexing and demodulation algorithms for an advanced satellite communication system on a hypercube. The mapping on a hypercube provides the high speed necessary for processing hundreds of single channel per carrier/frequency division multiple access (SCPC/FDMA) voice/data channels. Data demultiplexing and demodulation are parts of the recovery of the transmitted digital data in a MODEM. A demultiplexer comprises a filter bank followed by the computation of FFT. A demodulator primarily consists of circuits to recovery carrier signal, clock frequency and data. The computation of FFT on a hypercube is well established (Hwang and Briggs 1984). Therefore, this paper analyses the filter bank and carrier and data recovery algorithms to find an efficient mapping in a multiprocessor environment connected in a hypercubic configuration. A few models to implement these algorithms on a hypercube are provided. Comparison of the speed-up achieved on a hypercube vrsus that on a sequential computer is provided for the three models.     

Multiuser detection and diversity reception for asynchronous CDMA mobile communication

In CDMA mobile communication systems, multiple access interference can be canceled by multiuser detection technique. The Degradation by channel fading can be reduced by diversity reception. This paper investigates a family of multiuser receivers that combined decor-relating detection, antenna diversity and RAKE multipath diversity. The performance of the multiuser receivers is analyzed. The results demonstrate a significant increase in the performance of the receivers by using multiuser detection and diversity reception.     

An associative memory based on an electronic neural network architecture

A high-density matrix of α-Si resistors was made to demonstrate a new type of parallel-processing associative memory consisting of an interconnected array of analog amplifiers. The 22 × 22 resistor matrix was made using a technology compatible with conventional VLSI processing. This demonstration circuit can recall up to four 22- bit memories in 1 to 10 µs while correcting errors in the input word of at least 5 bits. This function is difficult to perform efficiently in conventional digital hardware and is the basis for solving a variety of pattern-recognition problems including vision and speech.     

Modeling robust asynchronous communication protocols withfinite-state machines

A.V. Aho et al. (Comput. Math. Applic., vol.8, p.205-14, 1982) used communicating finite-state machines to model synchronous protocols for reliable communication across unreliable channels. Their ideas are extended to modeling asynchronous protocols for communication across unreliable channels using finite-state machines communicating via an unreliable shared memory. Lower bounds on the size of machines and the number of symbols in the transmission alphabet required to achieve reliable communication are established. Two types of finite-state machines and two fault models for the shared memory are considered. In each case it is shown that there are robust protocols for deletion and insertion errors. It is also shown that there are no robust protocols for mutation errors. In contrast, in the synchronous case, robust protocols exist for all of these types of errors     

A neural network architecture for preattentive vision

Recent results towards development of a neural network architecture for general-purpose preattentive vision are summarized. The architecture contains two parallel subsystems, the boundary contour system (BCS) and the feature contour system (FCS), which interact together to generate a representation of form-and-color-and-depth. Emergent boundary segmentation within the BCS and featural filling-in within the FCS are emphasized within a monocular setting. Applications to the analysis of boundaries, textures, and smooth surfaces are described, as is a model for invariant brightness perception under variable illumination conditions. The theory shows how suitably defined parallel and hierarchical interactions overcome computational uncertainties that necessarily exist at early processing stages. Some of the psychophysical and neurophysiological data supporting the theory's predictions are mentioned     

Fine-grained neural architecture search for image super-resolution

Designing efficient deep neural networks has achieved great interest in image super-resolution (SR). However, exploring diverse network structures is computationally expensive. More importantly, each layer in a network has a distinct role that leads to the design of a specialized structure. In this work, we present a novel neural architecture search (NAS) algorithm that efficiently explores layer-wise structures. Specifically, we construct a supernet allowing flexibility in choosing the number of channels and per-channel activation functions according to the role of each layer. The search process runs efficiently via channel pruning since gradient descent jointly optimizes the Mult-Adds and the accuracy of the searched models. We facilitate estimating the model Mult-Adds in a differentiable manner using relaxations in the backward pass. The searched model, named FGNAS, outperforms the state-of-the-art NAS-based SR methods by a large margin.     

A network architecture for a geostationary communication satellite

An M-VSAT communication system envisioned by NASA would provide low data rate, direct-to-the-user communications services for interactive data, voice, facsimile, and video conferencing. Such a system would enhance current communications services and enable new services     

ATM-based transport architecture for multiservices wirelesspersonal communication networks

This paper presents an ATM-based transport architecture for next-generation multiservices personal communication networks (PCN). Such “multimedia capable” integrated services wireless networks are motivated by an anticipated demand for wireless extensions to future broadband networks. An ATM compatible wireless network concept capable of supporting a mix of broadband ISDN services including constant bit-rate (CBR), variable bit-rate (VBR), and packet data transport is explored from an architectural viewpoint. The proposed system uses a hierarchical ATM switching network for interconnection of PCN microcells, each of which is serviced by high-speed, shared-access radio links based on ATM-compatible cell, relay principles. Design issues related to the physical (modulation), media access control (MAC), and data-link layers of the ATM-based radio link are discussed, and preliminary technical approaches are identified in each case. An example multiservice dynamic reservation (MDR) TDMA media access protocol is then considered in further detail, and simulation results are presented for an example voice/data scenario with a proportion of time-critical (i.e., multimedia) packet data. Time-of-expiry (TOE) based queue service disciplines are also investigated as a mechanism for improving the quality-of-service (QoS) in this scenario