High-Performance and Low-Cost 40-Gb/s CWDM Optical Modules

High-performance and low-cost 40-Gb/s optical modules using four different wavelength uncooled 10-Gb/s distributed-feedback (DFB) lasers are proposed and demonstrated. The 40-Gb/s optical module was integrated with coarse wavelength division multiplexing (CWDM) thin-film filters which enabled four 10-Gb/s transmission channels output through a single fiber. The 10-Gb/s DFB laser was packaged by commercialized low-cost coaxial TO-Can technology. The results of the 40-Gb/s optical module showed that the output optical power was above ${-}1$ dBm per channel and the system power budget was 12 dB. The transmission distance with a single-mode fiber reached more than 30 km at a bit-error-rate of $10^{{-}9}$. Compared with conventional 40-Gb/s optical modules, the module is easy to fabricate and is low cost. This proposed high-performance 40-Gb/s CWDM optical module demonstrates not only the feasibility of a 30 km transmission, but also shows the low-cost possibility of ensuring the application of WDM-passive optical network fiber-to-the-home systems.      

WDM PON using 10-Gb/s DPSK downstream and re-modulated 10-Gb/s OOK upstream based on SOA

A signal remodulation scheme of 10-Gb/s differential phase-shift keying(DPSK) downstream and 10-Gb/s on-off keying(OOK) upstream using a semiconductor optical amplifier(SOA) and a Mach-Zehnder intensity modulator(MZ-IM) at the optical networking unit(ONU) side for wavelength division multiplexed passive optical network(WDM PON) is proposed.Simulation results indicate that error-free operation can be achieved in a 20-km transmission,and the receiver sensitivity of return-to-zero differential phase-shift keying(RZ-DPSK) is higher than nonreturn-to-zero differential phase-shift keying(NRZ-DPSK) in the proposed scheme.     

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

A current-mode bidirectional I/O buffer was designed, and the maximum effective bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enhance the operating speed, the voltage swing on the transmission line was reduced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-matching scheme was used to generate bias voltages, which adjust output resistance of the buffer to be equal to the characteristic impedance of the transmission line in spite of process variations. The chip was fabricated by using a 0.8-μm CMOS technology. The chip size was 500×330 μm², and the power consumption was 50 mW at a supply voltage of 3 V     

10-Gb/s transmission and beyond

The authors outline obstacles encountered in the development of 10-Gb/s (STM-64, OC-192) systems. Technologies to overcome these obstacles are presented and compared, taking into account real field environments. A perspective on 40-Gb/s systems technologies is also given     

10-Gb/s millimeter-wave signal generation using photodiode bias modulation

We present a simple 120-GHz-band millimeter-wave (MMW) modulation method that uses the bias-voltage dependence of unitraveling-carrier-photodiode output power, which we call photodiode (PD) bias modulation. We investigated the dependence of the output-power-saturation mechanisms on the bias voltage. We used a lowpass filter in the bias circuit to increase the modulation bandwidth, and the 3-dB modulation bandwidth was over 7 GHz. We demonstrated the modulation of 120-GHz MMW signals at a data rate of 10 Gb/s using PD bias modulation.     

A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.     

40-to-10-Gb/s demultiplexing using an electro-absorption sampling window

The demultiplexing experiment from a 40 Gb/s optical time-division multiplexing signal is completed by using electro- absorption sampling window based on electronic phase-locked loop circuit for clock recovery. Error-free demultiplexing is achieved when the launched optical power into electro-absorption sampling window reaches 5.5 dBm without optical filter following the EDFA.     

1.25-Gb/s bidirectional colorless WDM-PON based on RSOA using subcarrier detection and optical carrier suppression

A new architecture for bidirectional gigabit colorless wavelength division multiplexed-passive optical network system based on a reflective semiconductor optical amplifier is proposed. It uses techniques of both optical carrier suppression and subcarrier multiplexing. There is no impact of a downlink signal on an uplink one due to the wavelength reuse because a light from a single optical source is divided into two parts for uplink and downlink transmissions. One is modulated by a downlink signal and the other, which is transformed into two sidebands with a suppressed optical carrier, is utilized for an uplink transmission. An uplink data is recovered by subcarrier multiplexing technique. 1.25-Gb/s error-free transmissions of both uplink and downlink are demonstrated experimentally.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.     

Combining self-phase modulation and optimum modulation conditionsto improve the performance of 10-Gb/s transmission systems using MQWMach-Zehnder modulators

For 10-Gb/s transmission over nondispersion shifted fiber, the combined use of self-phase modulation (SPM) and joint optimization of the bias and modulation voltages to increase the dispersion limited transmission distance is considered for multiple quantum well Mach-Zehnder modulators. For the dual drive (push-pull) modulation format, the dependence of the receiver sensitivity on fiber length and average transmitted optical power is determined for both conventional and π phase-shift modulators with either symmetric or asymmetric Y-branch waveguides. When SPM is negligible and the optical extinction ratio is maximized, the modulator design must he considered carefully in order to increase the transmission distance. By combining SPM and optimum modulation conditions, the dependence of the system performance on the modulator design is reduced substantially. For an average transmitted optical power of 12.5 dBm, the receiver sensitivity for transmission over 140 km of fiber varies by only 0.3 dB for the different modulator designs. This compares with a variation of 3.1 dB for maximum extinction ratio modulation     

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization

A 5-6.4 Gb/s transceiver, consisting of a parallel 12-channel transmitter (Tx), 12-channel receiver (Rx), clock generators based on LC-VCO phase-locked loops (PLLs), and a clock recovery unit, was developed. The Tx has a five-tap pre-emphasis filter, and the Rx has an equalizer with an intersymbol interference (ISI) monitor. Monitoring the ISI enables fine adjustment of loss compensation. The pre-emphasis filter in the Tx and the equalizer in the Rx compensate for transmission losses of up to 20 dB at 6.4 Gb/s, respectively. Both the Tx and Rx channels, including the PLLs, are 3.92 mm/sup 2/ in area. The transmitter dissipates 150 mW/channel at 6.4 Gb/s when compensating for a loss of 20 dB, and the receiver 90 mW/channel when compensating for the same loss.     

High-reliability and low-dark-current 10-Gb/s planar superlatticeavalanche photodiodes

For compact and high-sensitivity 10 Gb/s optical receiver applications, we have developed low-dark-current planar-structure InAlGaAs-InAlAs superlattice avalanche photodiodes with a Ti-implanted guard-ring. The APDs exhibited dark current as low as 0.36 μA at a gain of 10. The temperature dependence of the dark current was confirmed to be in a sufficient level for practical 10-Gb/s applications. The APDs also exhibited a quantum efficiency of 67%, a gain-bandwidth-product of 110 GHz, a top 3-dB bandwidth of 15.2 GHz, and a minimum gain for 10-GHz bandwidth of 1.6. Preliminary aging test also showed a stable dark current operation after aging of over 2200 h at 200°C. These high-reliability, low-dark-current, high-speed, and wide-dynamic-range characteristics are promising for 10-Gb/s high-sensitivity optical receiver use     

Compensation of intrachannel nonlinearities in 40-Gb/s pseudolinear systems using optical-phase conjugation

In this paper intrachannel nonlinearities in a return-to-zero differential-phase-shift-keyed (RZ-DPSK) 40-Gb/s 32/spl times/100-km system are compensated in the absence of signal power symmetry using a single LiNbO/sub 3/ conjugator and results in two decades of improvement in bit-error rate (BER). The reduction of transmission impairments enables the reach of the system to be extended from 5200 to 6400 km with a measured BER =5/spl times/10/sup -4/. This paper also presents a first-order perturbation analysis that describes the effects of optical-phase conjugation and dispersion mapping on the optical field of pulses.     

Nonlinearity Limitations When Mixing 40-Gb/s Coherent PDM-QPSK Channels With Preexisting 10-Gb/s NRZ Channels

We investigate the penalties onto a 40-Gb/s polarization-division-multiplexing (PDM)-quadrature phase-shift keying caused by PDM, wavelength-division multiplexing and 10-Gb/s nonreturn-to-zero neighbor channels. Besides, we optimize the carrier phase estimation process and introduce bandgaps in the multiplex in order to contain limitations caused by cross nonlinear effects.     

10-Gb/s Operation of RSOA for WDM PON

We report on the 10-Gb/s operation of the reflective semiconductor optical amplifier (RSOA) for the next-generation wavelength-division-multiplexed passive optical network (WDM PON). The bandwidth of the RSOA used in this experiment is merely 2.2 GHz. Nevertheless, a clear eye opening is obtained at 10 Gb/s by using the electronic equalizer processed offline. We investigate the impacts of the network's operating conditions (such as the injection power to the RSOA and the fiber length) on the performances of these equalizers. The results show that the RSOA-based WDM PON is operable at 10 Gb/s and the maximum reach can be extended to ${>}$ 20 km with the help of the forward error correction codes.      

Demonstration of widely tunable single-chip 10-Gb/s laser-modulators using multiple-bandgap InGaAsP quantum-well intermixing

High-speed wavelength-agile laser-modulators were fabricated for the first time using a quantum-well intermixing processing platform for monolithic integration. Over 19-GHz 3-dB modulator bandwidth was achieved and 10-Gb/s error-free transmission was demonstrated through 75 km of standard fiber.     

10-Gb/s modulator drivers with local feedback networks

A novel intrinsic collector-base capacitance (C/sub CB/) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-/spl mu/m SiGe BiCMOS process could generate 9 V/sub PP/ differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V/sub PP/ in 0.18-/spl mu/m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.     

10-Gb/s external modulation in optical CPFSK format

We demonstrated a synchronous control technique for external optical modulation in a format of continuous-phase frequency-shift keying (CPFSK) at 10 Gb/s. In this method, the FSK signal in the upper- or lower-sideband state synchronously shifts to the other state at the timing when their phases are the same. We investigated the accuracy of the timing control required for the synchronous control. Experimental results show that the allowable timing misalignment to keep power penalty of the receiver sensitivity less than 1 dB was more than 25 ps, 25% of each bit period.     

10-Gb/s driver amplifier using a tapered gate line for improved input matching

The use of a tapered gate line in a distributed amplifier (DA) is investigated and applied to the design of a GaAs monolithic microwave integrated circuit 10-Gb/s optical driver amplifier. Improved input matching is achieved near the cutoff frequency by reducing the characteristic impedance successively along the gate line toward the termination. With the improved matching conditions, the voltage ripple on the final resistor termination is reduced. The degree of tapering that can be employed is limited by the low-frequency gain and matching requirements. Detailed analysis and simulation results are used to investigate the advantage of this technique. To demonstrate its practical use, the performance of a 10-Gb/s DA fabricated with Filtronic Compound Semiconductor's 0.5-/spl mu/m pseudomorphic high electron-mobility transistor technology is presented.