A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-$mu{hbox {m}}$ CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of $pm40 muhbox{V}$ . Experimental results indicate a temperature sensitivity of approximately 53 $muhbox{V}/^{circ}hbox{C}$ for a nominal reference voltage of 0.4 V over a temperature range of $-60 ^{circ}hbox{C}$–$140 ^{circ}hbox{C}$.      

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-$mu$m CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop $Sigma Delta$ modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of ${-}$70 dBc/Hz inband, ${-}$104 dBc/Hz at 200-kHz offset and ${-}$ 121 dBc/Hz at 1-MHz offset with a reference spur of ${-}$84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.      

A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair

A novel circuit topology suitable for the implementation of CMOS voltage-controlled oscillators (VCOs) at millimeter-wave frequencies is presented in this paper. By employing transmission line segments to transform the admittance of the additional cross-coupled pair, the proposed LC-tank VCO can sustain fundamental oscillation at a frequency close to the $f _{max}$ of the transistors. Using a standard 0.18 $muhbox{m}$ CMOS process, a V-band VCO is realized for demonstration. The fabricated circuit exhibits a frequency tuning range of 670 MHz in the vicinity of 63 GHz. The measured output power and phase noise at 1 MHz offset are $-hbox{15~dBm}$ and $-hbox{89~dBc}/hbox{Hz}$ , respectively. Operated at a 1.8 $~$V supply voltage, the VCO core and the output buffer consume a total DC current of 55 mA.      

Integrated Multilayered On-Chip Inductors for Compact CMOS RFICs and Their Use in a Miniature Distributed Low-Noise-Amplifier Design for Ultra-Wideband Applications

A novel multilayered vertically integrated inductor structure is developed for miniature CMOS RF integrated circuits, and its properties are investigated. The effect of mutual inductance both within and between adjacent multilayer inductors is also studied. A distributed low noise amplifier is designed by incorporating this novel inductor structure in a standard JAZZ 0.18-$mu$m RF/mixed signal CMOS process, demonstrating the significance of the proposed multilayered inductors in CMOS circuit miniaturization. The three-stage distributed amplifier occupies just 288$,times,$291 $mu$m or 0.08 mm $^{2}$ of die area, making it the smallest distributed amplifier reported to date. The circuit exhibits a relatively flat gain of 6 dB from 3.1 to 10.6 GHz with less than 0.5-dB ripple, with excellent input and output match of less than ${-}$ 12 and ${-}$25 dB, respectively. The noise figure is less than 5 dB to 14 GHz with only 2.7 dB across 8–10 GHz, while the power consumption is approximately 22 mW.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A high-frame rate duplex ultrasound biomicroscopy for small animal imaging in vivo

Much of the current knowledge of human cardiovascular pathologies and treatment strategies has been gained from understanding the cardiac physiologies and functions in small animal models, such as mice, rats, and zebrafish. In this paper, we present the development of a high-frame-rate duplex ultrasound biomicroscopy (UBM) capable of B-mode imaging and pulsed-wave (PW) Doppler measurement for in vivo cardiovascular investigation in small animals. A frame rate of 200 frames per second (fps) was accomplished at a view of 5 mm $times$ 8 mm, using a novel high-speed sector probe and specially designed lightweight transducers. In a reduced lateral view of 1.2 mm, a frame rate of 400 fps was achieved to examine more detailed cardiac motion. The UBM utilized transducers with different center frequencies (40–75 MHz) and geometries, which made it useful for various applications in small animal cardiac imaging. The highest spatial resolution the UBM achieved was 25 $mu$m $times$ 56 $mu$ m. In addition, the image-guided PW Doppler implemented in the UBM demonstrated the detection of the velocity of a moving wire as low as 0.1 mm/s, and flow in a polyimide tube as small as 200 $mu$ m in diameter. Furthermore, the UBM achieved a 15-$mu$ V minimal detectable signal and a 60-dB dynamic range using a low-cost PCB-based design. Finally, sample in vivo cardiac images of mouse and zebrafish hearts were given. These results showed that the UBM integrated with B-mode and PW Doppler is useful to investigate the pathophysiological mechanism in the cardiovascular studies.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.      

An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$98 dB THD

A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. Realized in a 0.18 $mu{hbox{m}}$ CMOS technology, it provides 81 dB SNDR, 82 dB dynamic range, and $-$98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 $~$V power supply (analog power 4.4 mW, digital power 3.7$~$ mW). Its figure-of-merit is 0.25 pJ/conversion-step, which is among the best reported for discrete-time delta-sigma ADCs in wideband applications.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

Delta-Sigma Modulation for Direct Digital Frequency Synthesis

This paper compares different $DeltaSigma$ modulation techniques for direct digital frequency synthesis (DDS). $DeltaSigma$ modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-$mu$m CMOS technology with core area of $1.7times 2.1 {hbox {mm}}^{2}$ and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain $DeltaSigma$ modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward $DeltaSigma$ modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

A 10$sim$ 15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration

Floating-point analog-to-digital converter (FADC) utilizes an up-front variable-gain amplifier (VGA) to enhance its low-level resolution. Although it is a single-path system, varying gain by switching circuit elements in and out modulates the gain and offset as in the multi-path time-interleaved ADC. For high-speed operation at all gain settings, a constant-bandwidth switched-capacitor VGA is implemented with variable-bandwidth opamps, and its gain and offset are digitally calibrated in background using signal-dependent pseudo-random noise (PN) dithering and chopping techniques. A three-stage VGA adjusts its gain instantly from $times$ 1 to $times$ 32 depending on the sampled input level, and improves the INL of a 10-bit ADC from 24 to 0.9 least significant bits (LSBs) at a 15-bit level for the low-level input. The resulting 10 $sim$ 15-bit 60-MS/s ADC needs no input sample-and-hold (S/H) stage, and achieves a system noise of $-$80 dBFS with a gain set to $times$ 32. A prototype chip in 0.18-$muhbox{m}$ CMOS occupies an active area of $3.0times 2.0 hbox{mm}^{2}$ , and consumes 300 mW at 1.8 V including digital calibration logic.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain $(K_{VCO})$ variation was developed. For small $K_{VCO}$ variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 $mu{rm m}$ CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has $-$ 113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.      

On Parallelepiped-Shaped Passbands for Multidimensional Nonseparable ${bf M}$th-Band Low-Pass Filters

The “shape” of the desired frequency passband is an important consideration in the design of nonseparable multidimensional ($M$ -D) filters in $M$-D multirate systems. For $M$-D ${bf M}$th-band filters, the passband shape should be chosen such that the ${bf M}$th-band constraint is satisfied. The most commonly used shape of the passband for $M$-D ${bf M}$ th-band low-pass filters is the so-called symmetric parallelepiped (SPD) ${rm SPD}(pi {bf M}^{- {rm T}})$ . In this paper, we consider the more general parallelepiped passband ${rm SPD}(pi {bf L} ^{rm T})$, and derive conditions on $ {bf L} $ such that the ${bf M}$ th-band constraint is satisfied. This result gives some flexibility in designing $M$-D ${bf M}$th-band filters with parallelepiped shapes other than the commonly used case of $ {bf L} = {bf M}^{- 1}$. We present design examples of 2-D ${bf M}$th-band filters to illustrate this flexibility in the choice of $ {bf L} $.      

Endurance Reliability of Multilevel-Cell Flash Memory Using a $ hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ Dual Charge Storage Layer

The mechanisms of programming/erasing (P/E) and endurance degradation have been investigated for multilevel-cell (MLC) Flash memories using a $hbox{Si}_{3}hbox{N}_{4}$ (NROM) or a $hbox{ZrO}_{2}/hbox{Si}_{3}hbox{N}_{4}$ dual charge storage layer (DCSL). Threshold-voltage $(V_{rm th})$ -level disturbance is found to be the major endurance degradation factor of NROM-type MLCs, whereas separated charge storage and step-up potential wells give rise to a superior $V_{rm th}$ -level controllability for DCSL MLCs. The programmed $V_{rm th}$ levels of DCSL MLCs are controlled by the spatial charge distribution, as well as the charge storage capacity of each storage layer, rather than the charge injection. As a result, DCSL MLCs show negligible $V_{rm th}$-level offsets ($ ≪ $ 0.2 V) that are maintained throughout the $hbox{10}^{5}$ P/E cycles, demonstrating significantly improved endurance reliability compared to NROM-type MLCs.      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Improved Bounds on the $L(2,1)$-Number of Direct and Strong Products of Graphs

The frequency assignment problem is to assign a frequency which is a nonnegative integer to each radio transmitter so that interfering transmitters are assigned frequencies whose separation is not in a set of disallowed separations. This frequency assignment problem can be modelled with vertex labelings of graphs. An $L(2,1)$-labeling of a graph $G$ is a function $f$ from the vertex set $V(G)$ to the set of all nonnegative integers such that $vert f(x)-f(y)vertgeq 2$ if $d(x,y)=1$ and $vert f(x)-f(y)vertgeq 1$ if $d(x,y)=2$ , where $d(x,y)$ denotes the distance between $x$ and $y$ in $G$. The $L(2,1)$ -labeling number $lambda(G)$ of $G$ is the smallest number $k$ such that $G$ has an $L(2,1)$-labeling with $max{f(v):vin V(G)}=k$. This paper considers the graph formed by the direct product and the strong product of two graphs and gets better bounds than those of KlavŽar and Špacapan with refined approaches.      

A 36 V Programmable Instrumentation Amplifier With Sub-20 $mu$V Offset and a CMRR in Excess of 120 dB at All Gain Settings

A 36 V capable programmable gain instrumentation amplifier (PGA) is presented with sub-20 $muhbox{V}$ offset, sub-0.2 $muhbox{V}/^{circ}{hbox{C}}$ offset drift and a common-mode rejection (CMRR) that exceeds 120 dB at all gain settings without any trimming. It is the first 36 V capable precision PGA implemented in a high-voltage CMOS process, which, in addition, incorporates several additional functions, such as the detection of input and output fault conditions, provisions for improving system-level settling time and an input switch network. All op-amps used in the PGA employ chopper stabilization with a notch filter that removes chopping glitches, leading to low offset and drift and no $1/f$ noise. The PGA has a total of 22 gain steps (binary steps between 1/8 to 128, each with an optional multiplying factor of 1 or 1.375) with better than 0.1% gain accuracy, $≪$0.001% nonlinearity and sub-2 ppm/C gain drift. The input switch network, in addition to acting as a 2-channel multiplexer, also enables various system-level diagnostic features. The PGA is implemented in a 0.35 $muhbox{m}$ CMOS process with a 36 V extension, has a 3.6 $times$ 2.4 mm chip area and consumes a total quiescent current of 3 mA.