A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-$mu$m CMOS

A fully integrated dual-conversion transmitter chain with an on-chip dipole antenna and an integer-N synthesizer operating in the 24-GHz Instrument, Scientific and Medical (ISM) band was fabricated in 0.13-mum CMOS. The choice of 24-GHz operation enables the integration of a 4-mm long antenna on chip. The transmitter chain can support data rate of 100 Mb/s. It provides 6-dBm output power to a 100-Omega load at 22.4 GHz with 152-mW power dissipation including that of a frequency synthesizer. At this output power level, the dual conversion architecture can mitigate the VCO pulling even when an antenna and a power amplifier are integrated on the same substrate as the VCO. The out-of-band emissions due to the modulation side lobes and image have been sufficiently suppressed. The stray emissions of local oscillator can also be reduced using circuit techniques. The signal from the transmitter has been picked up 95 meters away with a horn antenna, which suggests that wireless communications between a single chip radio and a base station 100 meters away is possible.     

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.     

3-GHz Silicon Photodiodes Integrated in a 0.18-$mu$m CMOS Technology

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of $70times 70 mu$m $^{2}$ fabricated in a 0.18- $mu$m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.      

Bumpless Interconnect of 6- $mu$m-Pitch Cu Electrodes at Room Temperature

Bumpless interconnect of 6-$mu{rm m}$-pitch Cu electrodes was realized at room temperature with the surface activated bonding (SAB) method. In this study, we propose a novel bumpless structure, where the electrodes and a surrounding Cu frame are fabricated with the same height to increase bond strength and demonstrate the feasibility of a sealing interconnection between Cu surfaces. The damascene process, assisted by the reactive ion beam etching (RIE), was used to fabricate the Cu structures. 923$thinspace$521 electrodes placed inside the frame were arranged into a spiral chain to enable the detection of the positions with insufficient interconnection by electrical resistance measurements. Using the SAB conditions optimized with simple chemo-mechanical polishing (CMP)-Cu film samples, we found that 744$thinspace$769 electrodes were successfully interconnected, except some specific lines near the frame, which might be due to sample preparation error rather than a bond defect. The mean contact resistance was below 0.08 $Omega$; a sealing effect was achieved at the frame structure because there was little increase in the contact resistance in high temperature storage testing performed at 150 $^{circ}{rm C}$ for 1000 h, in ambient air.      

Design and Properties of Phototransistor Photodetector in Standard 0.35- $mu$m SiGe BiCMOS Technology

In this paper, without altering any step of the commercial 0.35-mum SiGe BiCMOS process, a novel photodetector named phototransistor photodetector (PTPD) has been realized and demonstrated. The PTPD shows high photoresponsivity and its structure relaxes the tradeoff between sensitivity and speed. Responsivities of 9.5 A/W for 670 nm light and of 5.2 A/W for 850 nm light were achieved. The operation details of the PTPD are introduced in this paper. The device can be readily integrated with other on-chip circuits to form a high-performance optoelectronic IC. The low cost, the high performance, and the flexibility in optical-electrical design allow the SiGe PTPD to be used in many demanding applications.     

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-$mu$m CMOS

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18- $mu$m CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.      

A Low Voltage 0.35$mu$m CMOS FrequencyDivider With the Body Injection Technique

This letter proposes a new CMOS injection locked frequency divider (ILFD) fabricated in a 0.35 mum CMOS process. The ILFD circuit is realized with a cross-coupled CMOS LC-tank oscillator, and the injecticon is carried out through the bodies of cross- coupled transistors. The self-oscillating ILFD is injection-locked by second-(third-) harmonic input to obtain the division order of two (three). Measurement results show that at the supply voltage of 1.5 V and at the incident power of 10 dBm, the locking range is from the incident frequency 6.94 to 8.41 GHz in the divide-by-3 mode and the operation range is from the incident frequency 4.56 to 5.59 GHz in the divide-by-2 mode.     

Low-Threshold 1.3-$mu$m GaInNAs Quantum-Well Lasers Using Quaternary-Barrier Structures

GaInNAs quaternary-barrier structures, where indium is incorporated to achieve the lattice-matched condition, have been employed for 1.3-m GaInNAs-GaAs single- (SQW) and triple-quantum-well (TQW) lasers. Compared to a GaNAs ternary-barrier structure, photoluminescence results from the quaternary-barrier sample show improved optical properties. Threshold current densities have been achieved with the lowest values of 150 and 529 A/cm² for GaInNAs SQW and TQW lasers at room temperature, respectively.     

All-Silicon 1.55-$mu$m High-Resolution Photon Counting and Timing

We investigate the performances at 1.55- $mu{hbox{m}}$ wavelength of silicon single photon avalanche diodes (SPADs), demonstrating their suitable applicability in laser characterizations and ultra-sensitive autocorrelation measurements. We investigate the photon detection efficiency and the two-photon absorption process of both lightly doped thick SPADs and heavily doped thin SPADs. Finally, we report the accurate pulse-shape characterization of a 1.55- $mu{hbox{m}}$ pulsed laser by means of a thin silicon SPAD that exploits the best intrinsic time resolution of 25 ps with wide dynamic range and low measurement time.      

Optical Absorption Glucose Measurements Using 2.3-$mu$m Vertical-Cavity Semiconductor Lasers

Continuous glucose monitoring has been shown to help diabetes mellitus patients stabilize their glucose levels, leading to improved patient health. One promising technique for monitoring blood glucose concentration is to use optical absorption spectroscopy. This letter proposes the use of thermally tunable 2.3-mum vertical-cavity surface-emitting lasers to obtain blood absorption spectra. The partial least squares technique is used to determine the glucose concentration from the spectra obtained in aqueous glucose solutions.     

A 40-Gb/s Transimpedance Amplifier in 0.18-$mu$m CMOS Technology

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/P_de) of 180.1 GHzOmega/mW.     

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $mu$m CMOS

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.     

A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 $mu$m CMOS Technology

By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 kOmega and a -3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from -20 dBm to +0 dBm at a bit-error rate of 10^-12 with a 2³¹ -1 pseudorandom test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and - 3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.     

Characterization of the Resonant Third-Order Nonlinear Susceptibility of Si-Doped GaN–AlN Quantum Wells and Quantum Dots at 1.5 $mu$m

We report on the third-order optical nonlinearity of the e ₁ -e ₂ intersubband transition in GaN-AlN quantum wells and the s-p z intraband transition in GaN-AlN quantum dots, both of them in the spectral region around 1.5 mum. The results in terms of third-order susceptibility, together with the ultrafast nature of the nonlinear response, render these GaN-AlN nanostructures particularly suitable for optical switching and wavelength conversion applications.     

Two-Way Handshaking Circular Sequential $k$-Out-of- $n$ Congestion System

Many communication systems require a two-way, or three-way handshaking process to improve their dependability & authenticity in order to achieve a more successful operation. In this paper, we present a new two-way handshaking reliability model based upon threshold-based cryptography systems. Such systems require a two-way handshaking process to i) establish a group of participated servers in the first handshaking process, and ii) calculate a cipher with successfully connected servers collaboratively in the second handshaking process. When the servers are attempted, each server has three known connection probabilities in the following three states: i) successful, ii) breakdown, and iii) congested. These connection probabilities are unchanged in both handshaking processes. During the first handshaking process, we establish connections that more than servers are willing to participate. For the second handshaking process, the system becomes successful as soon as we can connect these servers successfully again. Because we need to connect servers successfully in the second handshaking process, we would rather connect additional servers besides the servers required to be connected successfully in the first handshaking process. This preference will minimize the chance that the system breaks down when fewer than servers can be reconnected successfully in the second handshaking process. We refer to this system as a Two-Way Handshaking Circular Sequential-out-of-Congestion (TWHCSknC) system. In this paper, we derived analytical formulas for the system's successful probability & average stop length, and we showed that the TWHCSknC system is a communication system with an efficient two-way handshaking process.     

A 0.6–2.7 GHz Semidynamic Frequency Divide-by-3 Utilizing Wideband RC Polyphase Filter in 0.18 $mu$m CMOS

A wideband complementary metal oxide semiconductor (CMOS) semidynamic frequency divide-by-3 covering more than two octave bandwidths is presented. The wideband operation without requiring a quadrature signal source is realized by employing a three-stage RC polyphase filter. The transfer function analysis on Type-II two- and three-stage polyphase filters is performed to provide analytic solutions of the peak phase error and peak attenuation. Implemented in 0.18 mum CMOS, the divide-by-3 operates over the input frequency range between 0.6 and 2.7 GHz while dissipating 15 mA from a 1.8 V supply.     

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

A 24 GHz Amplitude Monopulse Comparator in 0.13 $mu$m CMOS

This letter presents the design and implementation of a wideband 24 GHz amplitude monopulse comparator in 0.13 $mu$m CMOS technology. The circuit results in 9.6 dB gain in the sum channel at 24 GHz with a 3-dB bandwidth of 23.0–25.2 GHz, and a sum/difference ratio of $> 25$ dB at 20–26 GHz. The measured input P1 dB is ${-}14.4$ dBm at 24 GHz. The chip is only 0.55$,times,$ 0.50 mm$^{2}$ (without pads) and consumes 44 mA from a 1.5 V supply, including the input active baluns and the differential to single-ended output stages (28 mA without the input and output stages). To our knowledge, this is the first demonstration of a high performance mm-wave CMOS monopulse comparator RFIC.