一种低功耗的高速光接收器跨阻前置电路设计

为了降低芯片面积和功耗,提出了一种10 Gb/s光接收器跨阻前置放大电路。该电路采用了两个带有可调共源共栅（RGC）输入的交叉有源反馈结构,其中的跨阻放大器未使用电感,从而减少了芯片的总体尺寸。该跨阻前置电路采用0.13μm CMOS工艺设计而成,数据速率高达10 Gb/s。测试结果表明,相比其他类似电路,提出的电路芯片面积和功耗更小,芯片面积仅为0.072mm2,当电源电压为1.3 V时,功率损耗为9.1 mW,实测平均等效输入噪声电流谱密度为20pA/（0.1-10）Hz,且-3dB带宽为6.9 GHz。     

带有低噪声单端转差分电路的射频增益可控放大器

为了改进传统电路中单端转差分电路的噪声性能,提高传统射频可变增益放大器的覆盖范围和步进精度,该文设计了一种带有低噪声单端转差分电路的射频增益可控放大器。该文利用噪声抵消技术降低了噪声系数,利用电容交叉耦合技术展宽电路带宽,利用输出源级跟随器的增益可调功能实现更高的步进精度。电路采用0.18 mm CMOS工艺,1.8 V供电电源,在170-870 MHz频率信号输入下,可以实现最低3.8 dB的噪声系数,55 dB的动态范围,步进精度0.8 dB,消耗14.76 mW的功耗,面积800 mm×600 mm。测试结果表明在覆盖更宽的频段范围下,该文设计的射频可变增益放大器在消耗相同功率条件下与传统的单端转差分电路相比可以达到更低的噪声系数,同时整个可变增益放大器可以提供更高的步进精度。     

A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 $mu$ m CMOS

A fully integrated direct-conversion tuner is implemented in 0.13 $muhbox{m}$ CMOS technology. A broadband noise-canceling balun LNA with the proposed dual cross-coupling technique helps achieve an overall receiver noise figure from 3.7 to 4.3 dB while consuming only 3.6 mW. The proposed current-mode switching scheme improves the achievable SNIR with a gain step of 15 dB, providing IIP3 improvement of 18 dB and NF degradation of only 6 dB. Moreover, design trade-offs are carefully considered in designing the baseband circuit, which provides wide gain tuning and bandwidth accuracy with a DC offset residual less than 6 mV. The measured maximum SNR values are better than 30 dB over wide input power levels, ensuring robust reception in a mobile environment. All circuit blocks are operated at 1.2 V. As a result, the tuner consumes power as low as 114 mW in the continuous mode. This compact tuner supports both UHF and L- bands, and occupies only 7.2 $ {hbox{mm}}^{2}$ die area.      

Design of a 65?nm CMOS 8?GHz wideband: track-and-hold, for radio astronomy and cosmology applications

In modern millimeter and sub-millimeter communication systems, particle physics, neutrino astronomy, and for passive applications in radio astronomy or remote atmospheric sensing, the trend is to eliminate analog functional blocks, such as mixers and filters, by converting the signal into the digital domain as early as possible in the processing chain. Therefore, fast analog-to-digital converters (ADC) are needed. Track-and-hold (TAH) circuits can reduce time constraints by holding the analog input value while comparators are sampled, in order to minimize the aperture time errors. This article describes the design of a TAH using the 65?nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a ?3?dB input bandwidth wider than 8?GHz. At 8?GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178?mW and ?2?dB, respectively. The TAH core dissipates around 40?mW. The measured total harmonic distortion (THD) at Nyquist sampling conditions is about ?37?dB. The circuit die area is 1.1?mm2.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

超宽带延时幅相控制多功能芯片的设计

针对航空航天和卫星通信等设备的需求,介绍了一款超宽带延时幅相控制多功能芯片。该芯片集成了数字和微波电路,有T/R 开关、5 位数控延时器(10 ps 步进TTD)、5位数控衰减器(1 dB 步进ATT)、2 个行波放大器、均衡器及数字电路。基于GaAs E/D PHEMT 工艺研制出了芯片实物,芯片尺寸为4.5 mm*5.0 mm*0.07 mm。采用微波在片测试系统对该幅相控制多功能芯片进行了实际测试,在3 ~ 17 GHz 频段内实现了10~310 ps 延时范围,1~31 dB 衰减范围。测试结果显示,发射/接收增益大于2 dB,发射1 dB 压缩输出功率P1 dB_Tx大于12 dBm,接收1 dB 压缩输出功率P1 dB_Rx大于10 dBm,全态输入输出驻波均小于1.7,+5 V 下工作电流130 mA,-5 V 下工作电流12 mA。衰减器全态RMS 精度小于1.4 dB,全态附加调相小于±8°。延时器全态RMS 精度小于3 ps,全态附加调幅小于±1 dB。     

A re-configurable MASH 2-2 bandpass DQEFM for multi-standard applications

The design, analysis and implementation of a multi-stage noise shaping (MASH) bandpass modulator that employs a differentially quantized error feedback modulator (DQEFM) structure is described. The re-configurability, reduction of power-hungry active blocks and reduced sensitivity to circuit non-idealities makes this proposed bandpass modulator a suitable candidate for a digital intermediate frequency receiver system. The mathematical analysis and simulation results indicate the resemblance of the proposed modulator with the conventional sigma-delta modulator. The circuit level simulations indicate the better performance of the proposed modulator in terms of hardware complexity and power. The proposed cascaded modulator when implemented using 45nm CMOS process attains a signal-to-noise plus distortion ratio of 81.4 dB for a bandwidth of 200 kHz (GSM) and 61 dB for a bandwidth of 5 MHz (WCDMA). The circuit level simulation of the proposed bandpass architecture indicates a power consumption of 3.7 mW and 6.9 mW for GSM and WCDMA modes with 1V supply.     

具有带外抑制特性的Ka波段低功耗低噪声放大器

基于0.15μm GaAs赝配高电子迁移率晶体管(PHEMT)工艺,成功研制了一款30~34 GHz频带内具有带外抑制特性的低功耗低噪声放大器(LNA)微波单片集成电路(MMIC)。该MMIC集成了滤波器和LNA,其中滤波器采用陷波器结构,可实现较低的插入损耗和较好的带外抑制特性;LNA采用单电源和电流复用结构,实现较高的增益和较低的功耗。测试结果表明,该MMIC芯片在30~34 GHz频带内,增益大于28 dB,噪声系数小于2.8 dB,功耗小于60 mW,在17~19 GHz频带内带外抑制比小于-35 dBc。芯片尺寸为2.40 mm×1.00 mm。该LNA MMIC可应用于毫米波T/R系统中。     

基于混合集成的高增益光接收模块北大核心

针对光载无线通信(RoF)系统对高增益、小型化光接收模块(ROSA)的需求,基于混合集成技术,设计并制作了一种高增益的四通道ROSA器件,尺寸为20.0 mm×14.0 mm×5.9 mm。模块内集成了低噪声放大器(LNA)芯片以提高射频信号增益,建立了射频信号传输电路,并对器件特性进行了仿真分析。经测试,器件的射频信号增益达14 dB,-3 dB带宽为23 GHz,在1550 nm波长的入射光下,器件的响应度为0.81 A/W,相邻信道之间的射频信号串扰小于-40 dB。该模块对于减小RoF系统的体积和功耗具有重要意义。     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

60-GHz-band coplanar MMIC active filters

This paper presents the design and performance of 60-GHz-band coplanar monolithic microwave integrated circuit (MMIC) active filters. To compensate for the loss of the passive filter, a resonator composed of a quarter-wavelength line is terminated by a circuit with a constant negative resistance over a wide frequency band. Cross-coupling is introduced to make the attenuation poles on both sides of the passband. We develop two types of two-stage filter: one with medium bandwidth and the other with narrow bandwidth. The former shows an insertion loss of 3.0 dB with a 3-dB bandwidth of 2.6 GHz and a rejection of larger than 20 dB at a 3-GHz separation from a center frequency of 65.0 GHz. This filter also shows a noise figure of 10.5 dB. The latter filter shows an insertion loss of 2.8 dB with a 10-dB bandwidth of 2.1 GHz at a center frequency of 65.0 GHz. It also shows an output power of 5.0 dBm at a 1-dB compression point. The loss variation due to temperature variation is successfully compensated using a gate bias control circuit. The size of the MMIC filters is 2.5 mm/spl times/1.1 mm.     

2～20GHz分布式单片放大器设计

介绍了一种采用0.15μm GaAs PHEMT工艺设计加工的2～20 GHz宽带单片放大器,为了提高电路的整体增益和带宽,在设计电路时采用两级级联分布式结构。此种电路结构不仅能够增加整体电路的增益和带宽,还可以提高电路的反向隔离,获得更低的噪声系数。利用Agilent ADS仿真设计软件对整体电路的原理图和版图进行仿真优化设计。后期电路在中国电子科技集团公司第十三研究所砷化镓工艺线上加工完成。电路性能指标:在2～20 GHz工作频率范围内,小信号增益>13.5 dB;输入输出回波损耗<-9 dB;噪声系数<4.0 dB;P-1>13 dBm。放大器的工作电压5 V,功耗400 mW,芯片面积为3.00 mm×1.6 mm。     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

Improved clock buffer with high PSRR for SC circuit applications

Clock feedthrough in SC circuits results in low PSRR figures, incompatible with high-performance signal processing. A high-PSRR CMOS clock buffer is presented here, which blocks this power supply (PS) noise coupling path. The presented circuit is a significant improvement over an earlier circuit proposed by the same author, but having a PSRR of over 40 dB now.<>     

A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications

This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz.     

10Gb/s光接收机跨阻前置放大器芯片设计研究

采用0.18 μm BiCMOS工艺设计并实现了一种高增益、低噪声、宽带宽以及大输入动态范围的光接收机跨阻前置放大器.在寄生电容为250 fF的情况下,采用全集成的四级放大电路,合理实现了上述各项参数指标间的折中.测试结果表明:放大器单端跨阻增益为73 dB,-3 dB带宽为7.6 GHz,灵敏度低至-20.44 dBm,功耗为74 mW,最大差分输出电压为200 mV,最大输入饱和光电流峰-峰值为1 mA,等效输入噪声为17.1 pA/√Hz,芯片面积为800 μ.m×950μm.     

Active Stabilization of Crystal Oscillator FM Noise at UHF Using a Dielectric Resonator (Short Papers)

A low-noise 600-MHz crystal oscillator circuit is described. It uses a dielectric oscillator as the dispersive element of a discriminator in an active frequency stabilization loop which reduces the near-carrier FM noise. The innovation in the circuit is an essentially noiseless active carrier suppression loop, which allows maximum utilization of a low-noise RF amplifier to reduce the discriminator threshold (Delta f/sub rms/) to 2.5x10-5 Hz in a 1-Hz bandwidth. The FM noise 1 kHz from the carrier was reduced by 44 dB to this threshold, equivalent to a phase-noise spectral density of -152 dBc/Hz.     

GaAs-based high-gain direct-coupled distributed preamplifier using active feedback topology

A single-chip ultra-high gain distributed amplifier (DA) was developed using commercial GaAs PHEMT foundry for 40-Gb/s base band applications. Two seven-section DAs are directly coupled using a lumped dc level-shift circuit. The dc bias level of the second-stage DA can be tuned using the level-shift circuit for optimum gain. The gain of each DA stage has been optimized using a novel active feedback cascode topology, which allows the gain bandwidth product to be maximized while avoiding instability problems. The fabricated single-chip DA with a size of 2.1 mm /spl times/ 2.3 mm showed a high gain of 28 dB, and an average noise figure of 4.6 dB with a 41 GHz bandwidth. The corresponding transimpedance gain was 62 dB/spl Omega/ and the input noise current density was 14.5 pA//spl radic/Hz. The gain bandwidth product (GBWP) is 1030 GHz, which corresponds to the highest performance using GaAs technology for 40 Gb/s applications.     

A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 Vbattery-operated systems

A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V_pp output voltage is presented. A measured p-weighted noise of 120 μV_rms leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm ² in a 0.8 μm CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply