Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect

In this paper, we developed a hermetic wafer level packaging for MEMS devices. Au–Sn eutectic bonding technology in a relatively low temperature is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of 1 mm × 1 mm × 700 μm, and a square loop Au–Sn metallization of 70 μm in width for hermetic sealing. The robustness of the package is confirmed by several tests such as shear strength test, reliability tests, and hermeticity test. The reliability issues of Au–Sn bonding technology, and copper through-wafer interconnection are discussed, and design considerations to improve the reliability are also presented. By applying O₂ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface. The mechanical effects of copper through-vias are also investigated numerically and experimentally. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, copper diffusion phenomenon, and cleaning process. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Single-sided piercing riveting for adhesive bonding in vehicle body assembly

With increasing use of advanced high strength, lightweight materials and alternative vehicle architectures, materials joining issues have become increasingly important in automotive vehicle body assembly. Among the various joining methods, adhesive bonding is one of the important techniques for joining dissimilar materials in vehicle body assembly. During curing of the adhesive, it is necessary to fix and control the gap between the sheet panels to ensure the bonding strength and geometric quality. In this paper, a novel process, the single-sided piercing riveting (SSPR), is proposed for fixing and controlling the gap between the sheet panels during adhesive bonding of vehicle body assembly. The SSPR is a cold forming process for joining two or more sheet parts by driving a specifically designed U-shaped rivet using an impact force. The SSPR process is easy and convenient to implement without the need of a direct back support, and can meet the limited space requirement of vehicle body assembly. Joining experiments and performance tests were carried out to validate the effectiveness of the SSPR process. Performance comparison with other joining methods shows that mechanical properties of the lap-shear SSPR-bonded joints are superior to that of the SPR and SPR-bonded lap-shear joints.     

Power delivery and locomotion of untethered microactuators

The ability for a device to locomote freely on a surface requires the ability to deliver power in a way that does not restrain the device's motion. This paper presents a MEMS actuator that operates free of any physically restraining tethers. We show how a capacitive coupling can be used to deliver power to untethered MEMS devices, independently of the position and orientation of those devices. Then, we provide a simple mechanical release process for detaching these MEMS devices from the fabrication substrate once chemical processing is complete. To produce these untethered microactuators in a batch-compatible manner while leveraging existing MEMS infrastructure, we have devised a novel postprocessing sequence for a standard MEMS multiproject wafer process. Through the use of this sequence, we show how to add, post hoc , a layer of dielectric between two previously deposited polysilicon films. We have demonstrated the effectiveness of these techniques through the successful fabrication and operation of untethered scratch drive actuators. Locomotion of these actuators is controlled by frequency modulation, and the devices achieve maximum speeds of over 1.5 mm/s.     

Fabrication of a freestanding micro mechanical structure using electroplated thick metal with a HAR SU-8 mold

In this thesis, fabrication technology of a freestanding micro mechanical structure using electroplated thick metal with a high-aspect-ratio SU-8 mold was studied. A cost-effective fabrication process using electroplating with the SU-8 mold was developed without expensive equipment and materials such as deep reactive-ion etching (DRIE) or a silicon-on-insulator (SOI) wafer. The process factors and methods for the removal of SU-8 were studied as a key technique of the thick metal micro mechanical structure. A novel method that removes cross-linked SU-8 completely without leaving remnants of the resist or altering the electroplated microstructure was utilized. The experimental data pertaining to the relationship between the geometric features and the parameters of the removal process are summarized. Based on the established SU-8 removal process, an electroplated nickel comb structure with high-aspect-ratio SU-8 mold was fabricated in a cost-effective manner. In addition, a freestanding micro mechanical structure without a sacrificial layer was successfully realized. The in-plane free movements of the released freestanding structure are demonstrated by electromagnetic actuation. This research implies that various types of MEMS devices can be developed at a low-cost with design flexibility.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Fabrication of a polymeric tapered HARMs array utilizing a low-cost nickel electroplated mold insert

A simple low-cost technique has been developed to fabricate a mold insert for replicating polymeric tapered high aspect ratio microstructures. A backside exposure technique is used to first obtain a tapered sidewall structure as an electroplating mold in SU-8 photoresist on a glass wafer. Nickel electroplating is utilized to form the mold insert. The lowest average surface roughness of the nickel mold insert on the side that interfaces with the glass wafer during electroplating is measured to be 7.02 nm. A novel technique involving use of titanium putty is introduced here to reduce cost and effort required to fabricate the mold insert. Replication of tapered microstructures in polymeric materials utilizing the fabricated mold insert is demonstrated here in polydimethylsiloxane by a direct molding process and in polymethyl methacrylate by hot embossing. The fabrication details for the mold insert are described. Advantages and disadvantages of the use of titanium putty for achieving superior metal surface finish are given.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Precision passive mechanical alignment of wafers

A passive mechanical wafer alignment technique, capable of micron and better alignment accuracy, was developed, fabricated and tested. This technique is based on the principle of elastic averaging: It uses mating pyramid (convex) and groove (concave) elements, which have been previously patterned on the wafers, to passively align wafers to each other as they are stacked. The concave and convex elements were micro machined on 4-in (100) silicon wafers using wet anisotropic (KOH) etching and deep reactive ion etching. Submicron repeatability and accuracy on the order of one micron were shown through testing. Repeatability and accuracy were also measured as a function of the number of engaged elements. Submicrometer repeatability was achieved with as little as eight mating elements. Potential applications of this technique are precision alignment for bonding of multiwafer MEMS devices and three-dimensional (3-D) interconnect integrated circuits (ICs), as well as one-step alignment for simultaneous bonding of multiple wafer stacks. Future work will focus on minimizing the size of the elements.     

基于硅晶圆键合工艺的MEMS电容式超声传感器设计

针对目前电容超声传感器多采用表面工艺制备,存在振膜应力大、厚度均匀性控制差且表面需要沉积分立电极而造成传感器灵敏度低、归一化位移小、频率易偏差的缺点,提出基于硅晶圆键合工艺的MEMS电容超声传感器。采用应力小、厚度均匀的SOI顶层硅作为敏感单元的一体化全振微传感薄膜,无需沉积分立电极,易于加工且频率偏差小。通过下电极的区域化定义及巧妙互联,避免了非活跃区的寄生电容。通过ANSYS及MATLAB对所设计的5种工作频率在124 kHz～484 kHz之间、满足水下成像需求的传感器结构进行性能分析,表明传感器的电容变化量为650.62 fF/Pa～10.827 fF/Pa,满足现有条件的信号检测,输出电压灵敏度可达1.700 mV/Pa。与同频率指标的传统基于牺牲工艺而制备的金属-氮化膜堆栈结构对比表明,本结构频率可预测性高,偏差仅为0.0535%;振膜变形更均匀,归一化位移提高0.0432%以上;灵敏度平均提高11.9249 dB。     

Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology

Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating large CMUTs, offers advantages over the traditionally micromachined CMUTs. First, forming a vacuum-sealed cavity is relatively easy since the wafer bonding is performed in a vacuum chamber. Second, this process enables better control over the gap height, making it possible to fabricate very small gaps (less than 0.1 /spl mu/m). Third, since the membrane is made of single crystal silicon, it is possible to predict and control the mechanical properties of the membrane to within 5%. Finally, the number of process steps involved in making a CMUT has been reduced from 22 to 15, shortening the device turn-around time. All of these advantages provide repeatable fabrication of CMUTs featuring predictable center frequency, bandwidth, and collapse voltage.     

一种MEMS薄膜材料的力学性能测试方法

介绍了一种用于MEMS薄膜材料力学特性测试的单轴拉伸试验方法。其特点是微小试件两端固定,且与加载机构集成在基片上,从而可减少操作工作量,提高对准精度。整个机构以微细加工方法制成,硅类试件以干法蚀刻成型,金属类试件以电镀方法成型,其余加载机构以湿法刻蚀制成。试验表明:使用此机构可以简单且高精度地对薄膜试件进行拉伸试验,获得多项力学性能参数,从而为MEMS器件设计和分析提供可靠的理论基础。     

Laser Bonding of Glass to Silicon Using Polymer for Microsystems Packaging

Laser joining is a promising technique for wafer-level bonding. It avoids subjecting the complete microelectromechanical system (MEMS) package to a high temperature and/or the high electric field associated with conventional wafer-level bonding processes, using the laser to provide only localized heating. We demonstrate that a benzocyclobutene (BCB) polymer, used as an intermediate bonding layer in the packaging of MEMS devices, can be satisfactorily cured by using laser heating with a substantial reduction of curing time compared with an oven-based process. A glass-on-silicon (Si) cavity bonded with a BCB ring can be produced in a few seconds at a typical laser intensity of 1 W/mm² resulting in a local temperature of ~300degC. Hermeticity and bond strength tests show that such cavities have similar or better performance than cavities sealed by commercial substrate bonders. The influence of exposure time, laser power, and applied pressure on the degree of cure, bond strength, and hermeticity is investigated. The concept of using a large area uniform laser beam together with a simple mirror mask is tested, demonstrating that such a mask is capable of protecting the center of the cavity from the laser beam; however, to prevent lateral heating via conduction through the Si, a high-conductivity heat sink is required to be in good thermal contact with the rear of the Si.     

Manufacturing costs for microsystems/MEMS using high aspect ratio microfabrication techniques

The emphasis on high aspect ratio micromachining techniques for microsystems/MEMS has been mainly to achieve novel devices with, for example, high sensing or actuation performance. Often these utilize deep structures (100–1,000 μm) with vertical wall layers but with relatively modest spatial resolution (1–10 μm). As these techniques move from research to industrial manufacture, the capital cost of the equipment and the cost of device manufacture become important, particularly where more than one micromachining technique can meet the performance requirements. This paper investigates the layer-processing costs associated with the principal high aspect ratio micromachining techniques used in microsystems/MEMS fabrication, particularly silicon surface micromachining, wet bulk etching, wafer bonding, Deep Reactive Ion Etching, excimer laser micromachining, UV LIGA and X-ray LIGA. A cost model (MEMSCOST) has been developed which takes the financial, operational and machine-dependent parameters of the different manufacturing techniques as inputs and calculates the layer-processing costs at the wafer and chip level as a function of demand volume. The associated operational and investment costs are also calculated. Cost reductions through increases in the wafer size and decreases in chip area are investigated, and the importance of packaging costs demonstrated.     

TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.     

Fabrication of helically perforated gold, nickel, and polystyrene thin films

Helical microstructures are of interest for MEMS devices because of their spring-like shape. However, helices with micron and submicron dimensions are difficult to engineer using conventional processing techniques where patterning is accomplished lithographically. In this paper, we report the fabrication of porous gold, nickel, and polystyrene thin films with helical pore architectures. All films were made using a replication process, in which a thin film comprised of independent helical microstructures acted as the template. Filling of the template with metals was achieved by electroplating through the microstructures, whereas filling with polystyrene was achieved by capillary action. Porous films were produced from these composites by wet etch removal of the template material. Typical helical pores were on the order of 100 nm in diameter and extended through a film 1 /spl mu/m to 2 /spl mu/m thick. These films were generally more robust than the films from which they were templated, since they consisted of a solid network with helical pores rather than individual structures. Polymer and metal films with helical pores could be used for sensor and catalytic devices that take advantage of the chemical properties of these materials. Polymer films are also of interest for mechanical sensor and actuator devices since they are expected to be more compliant than both traditional MEMS materials and the films from which they were templated.     

一种用于测试坡莫合金薄膜机械性能的拉伸模型

坡莫合金(Ni80Fe20)薄膜是微机电系统常用的磁性材料之一.介绍了一种用于测试其机械性能的单轴拉伸试验模型.此模型的特点是微小试件两端固定、且与加载机构集成在基片上,从而可减少操作工作量、提高对准精度.整个机构以微细加工方法制成:坡莫合金拉伸试件以光刻和电镀技术成型,其余的加载机构以湿法蚀刻制成.实验表明:使用此机构可以简单且高精度地对薄膜试件进行拉伸试验,获得多项力学性能参数,从而为MEMS器件设计和分析提供可靠的理论基础.     

适用于RF MEMS能量耦合传输的高Q值电感

利用MEMS微电镀工艺技术制作了一种新型的适用于RF MEMS能量耦合传输的高Q值电感,采用ANSOFT公司的HFSS优化平面螺旋电感的结构。在具有高电阻率的玻璃衬底上溅射0.5μm的铜层作为下电极;PECVD淀积厚度为1μmSiO2作为中间介质层;在介质层上结合厚胶光刻技术电镀厚为22μm的铜作为电感线圈。这套电感制作工艺流程简单、易于与IC制备工艺集成。本文制备的微机械电感在微型植入系统中具有广阔的应用前景。测量结果表明:当工作频率在1GHz左右时,微电感的电感值达到55nH,Q值最大可达到25。