Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO₂ gives the best results for low power and high-speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n-CNTFET and varied for p-CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N-curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.     

Design and analysis of a gate-all-around CNTFET-based SRAM cell

This paper proposes a highly stable and low power 6-T static random access memory (SRAM) cell design using a gate-all-around carbon nanotube field effect transistor (GAA-CNTFET). The 6-T SRAM cell is designed and analyzed in HSPICE for different performance metrics viz. SNM, read SNM, write SNM, delay, and leakage power for both the top gate CNTFET and the GAA-CNTFET. The effect of variation of the power supply voltage on the leakage current is also presented, and it was found that the GAA-CNTFET accounts for low power dissipation at higher supply voltage. The 6-T SRAM cell is analyzed for different flat band conditions of the p-type CNTFET taking flatband of the n-type as constant, which is called a dual flat band voltage technique. Through simulations, it is found that by increasing the flatband voltage of a p-type CNTFET, the SRAM gives better performance. The dual flatband variation technique is compared with dual chirality technique, and it is observed that both techniques give the same results.     

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V_DD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V_DD and BLB is discharged to the ground. The proposed non‐V_DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.     

A data aware 9T static random access memory cell for low power consumption and improved stability

Reducing the power consumption in static random access memory can significantly improve the system power efficiency, reliability, and performance. In this paper, we propose a data aware static random access memory cell to reduce the power consumption during read and write operation. The proposed cell contains nine transistors with separate read/write ports. The write operation in the proposed cell is controlled by an additional write signal instead of word line. Because of isolation of the storage nodes with bit lines, read signal‐to‐noise margin is equal to ideal hold signal‐to‐noise margin of the conventional cell. The proposed cell saves approximately more than 43% active power compared with the 6T cell and other published cells. The proposed cell gives faster write access and low leakage current compared with the conventional and other cells. About 99% standby column power reduction, with 128 cells, is observed in the proposed cell. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and statistical analysis of low power and high speed 10T static random access memory cell

Static random access memory (SRAM)-based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems. Several SRAM cells had been developed to address the stability and power loss problem. But still, it is a challenge to achieve balance performance among all the parameters of the SRAM cell for sub-nanometer technology. This paper proposes a novel SRAM cell, which is having comparatively less total, static power loss, less delay, and high stability compared with the conventional cells for 45-nm complementary metal-oxide-semiconductor (CMOS) technology. The total power cost of the proposed 10T cell has been reduced by 90.3%, 85.84%, 51.02%, and 90.9% compared with 6T, N-controlled (NC), 10T sub, and 10T, respectively. Similarly, the static power cost of the proposed cell has been reduced by 55.17%, 5.72%, -41.6%, and 52.9% compared with 6T, NC, 10T-sub, and 10T, respectively. The proposed cell provides better stability, less delay, and comparable area compared with other considered 10T cells. Finally, the Monte Carlo (MC) simulation and process analysis of SRAM cells validate the efficiency of the proposed 10T cell.     

Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology

A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at V_DD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.     

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.     

New SRAM design using body bias technique for low‐power and high‐speed applications

In this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.     

SRAM circuit-failure modeling and reliability simulation with SPICE

Based on some new accelerated lifetime models and failure equivalent circuit modeling techniques for the common semiconductor wear out mechanisms, simulation program with integrated circuit emphasis (SPICE) can be used to characterize CMOS VLSI circuit failure behaviors and perform reliability simulation. This paper used a simple SRAM circuit as an example to demonstrate how to apply SPICE to circuit reliability modeling, simulation, analysis, and design. The SRAM circuit, implemented with a commercial 0.25-/spl mu/m technology, consists of functional blocks of 1-bit six-transistor cell, precharge, read/write control, and sense amplifier. The SRAM operation sequence of "write 0, read 0, write 1, read 1" was first simulated in SPICE to obtain the terminal voltage and current stress profiles of each transistor. Then, normalized lifetimes of all transistors in terms of each failure mechanism were calculated with the corresponding accelerated lifetime models. These lifetime values were sorted to single out the most damaged transistors. Finally, the selected transistors were substituted with failure equivalent circuit models, and SPICE simulations were performed again to characterize the circuit performance, functionality, and failure behaviors. The simulation shows that the 0.25-/spl mu/m technology, hot-carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) had significant effects on SRAM-cell stability and voltage-transfer characteristics, while negative bias temperature instability (NBTI) mainly degraded the cell transition speed when the cell state flipped. This illustrative SRAM simulation work proves that, with SPICE and the failure equivalent circuit models, circuit designers can better understand the damage effects of HCI/TDDB/NBTI on the circuit operation, quickly estimate the circuit lifetime, make appropriate performance/reliability tradeoffs, and formulate practical design guidelines to improve the circuit reliability.     

Write-enhanced and radiation-hardened SRAM for multi-node upset tolerance in space-radiation environments

As transistor feature size is scaling down, the probability of charge sharing in a space-radiation environment increases because of the reduced distance between adjacent transistors. The single-event multiple-node upset (SEMNU) caused by charge sharing is a major source of data errors in high-density static random-access memory (SRAM). In this paper, a radiation-hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD-12T, RSP14T, SEA14T, We-Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC-14T cell saves 8.47%, 91.34%, 162.71%, -20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read-delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write-delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation-intensive space environment.     

基于深度强化学习的无人机辅助物联网多目标优化

无人机辅助无线供电物联网是一种创新的网络架构,利用无人机作为能量传输中介,能够解决物联网设备电力供应 的限制和局限性。针对无人机辅助无线供电物联网网络中多目标控制策略学习的问题,提出了一种基于深度强化学习的多 目标双延迟深度确定性策略梯度(MOTD3) 算法,旨在满足偏航角、飞行速度以及发射功率约束条件下,实现总数据速率、总 收获能量最大化以及能耗和悬停时间最小化的多目标联合优化,同时因需求动态变化无人机进行在线路径规划。仿真结果 表明,该算法在保证良好的收敛情况和稳定性前提下,较其他算法在总数据速率、总收获能量、能耗与悬停时间方面分别提高 14.7%、10.6%、6.1%和10.3%,且具有较强泛化能力,可适用于实际中不同通信场景。     

Circuits simulation of switch devices furnished with gain cell combined to FeRAM

Abstract

This paper has described a new concept on programmable switch device furnished with gain cell combined to FeRAM. Compared with memories but ferroelectric memories under many aspects, they have even been favorably labeled the ideal memory because of their non-volatility, ease of programming and operation by low voltage. As the programming switch, which is very attractive for logic application, SRAM, anti-fuse, flash type devices are well known. They have been required that satisfy non-volatility and low-voltage programming simultaneously. Some structures with ferroelectric material have been proposed and studied as solution of these problems. However, it seemed hard that these type devices are realized now from a viewpoint of fabrication process and low voltage operation. Therefore, we propose a new switch device furnished with gain cell combined to FeRAM. We have studied and simulated this switch device by SPICE. This basic circuit is composed of two blocks. One is switching block that includes gain cell, and the other is memory block that is FeRAM. Circuits, which we designed, amplify bit line's voltage up to Vdd or ground at sense amplification according to FeRAM data. The bit line voltage determines the logic state for gate electrode of switch transistor. The way to read is destructive read out. However, we can transfer information of bit line voltage during plate line is low-level voltage. The way to write FeRAM is similar to conventional way. It is revealed that the basic circuit with FeRAM connected gain cell could work correctly in simulation. In addition, this kind of device is hopeful of many logic applications.     

A 1.8 V 4 k FeRAM Chip Using 0.2 u Process and Novel Design Techniques

Due to the increasing demand for high speed, low voltage or low power applications, non-volatile memory becomes even more important and more challenging as technology advances. With ferroelectric memories, which provides fast write and fast read with relatively low power, the challenge is to provide a ferroelectric random access memory (FeRAM) chip that operates at low voltages with the smallest geometry available in the technology. In this paper, we present a 1.8 V 4 k bit ferroelectric memory chip design, with emphasis on core/core control, bit:cell determination and key circuit design as well as simulation results based on a 0.2 u CMOS double level metal process and ferroelectric process parameter assumptions.     

电力系统测控仪表中数据存储方案设计

对于故障数据、重要的实时数据以及配置参数等关键数据,常规的保存方法是利用EEPROM,SRAM＋电池或者NVRAM等。MSP430F149单片杌内部有60kB的F1ash模块,该模块可以在应用中执行写操作;铁电存储器（FRAM）有读写无延时、擦写次数多等优点,利用MSP430F149单片机内Hash模块和FRAM存储器的特点,采用缓冲思想,设计了一种应用于电力参数监测仪表中的数据存储方案,并应用到了实际开发的产品中,取得了较好的效果。     

配电网调度监测数据的多线程集群共享内存折叠压缩方法

针对配电网中数据指数增长造成的读写时延越来越长的问题,提出一种多线程集群共享内存折叠压缩新方法。将数据结构扁平化处理融入于数据压缩之中,通过启用内存折叠方法,在写入内存过程中消除数据冗余,改变数据结构,减少刷新到磁盘的次数,同时缓解磁盘块缓存的压力,从而提高对数据的读写性能,以千万条数据记录的某动车段10kV配电网远动调度监控系统实测数据为例,搭建4个节点测试集群,进行集群内存压缩导入延时测试与读写性能测试。实验结果表明,启用内存压缩能优化内存结构,提升调度监测数据库的读写性能。     

Fabrication of 1K-Bit 1T2C-Type Ferroelectric Memory Cell Array

A 1K-bit 1T2C-type ferroelectric memory array has been designed and fabricated by combination of a 0.35 μm gate length CMOS process and a 3 μm design rule ferroelectric process. The write and readout operation in a 1K-bit 1T2C-type memory array cell has been confirmed experimentally.     

A Current-Gain Scheme for High Density and Low Voltage FeRAM

The proposed current-gain scheme provides a key technical solution for a high density, low cost and high performance ferroelectric random access memory. The proposed sensing scheme shows maximum sensing-signal window because of divided sub-bitline (SBL) structure. The unit cell array section is composed of the cell array of 64 rows and 128 columns with SBL, SBL switch (SBSW) devices and current-gain transistor (CGT) device. The global main bitline (MBL) is biased by MBL sensing load (MSL) device and connected to common MBL bus (CMB) through block selection switch (BSS) device. The device sizes of CGT and MSL devices are key factors for determining the transfer characteristics of SBL and MBL. The 128 sense amplifiers in peripheral circuit region are shared to all cell array blocks through CMB with 128 MBL columns of each cell array block. The address access time of the 16 Mb chip is evaluated to less than 70 ns at 3 V.     

Cross-point memory design challenges and survey of selector device characteristics

In this survey, the design challenges of cross-point memory arrays with emerging nonvolatile memory technologies are discussed. In particular, the write/read scheme for cross-point memory and the associated problems such as voltage drop along interconnect and sneak path current via unselected cells are analyzed. The write voltage margin and power consumption, as well as the read-current sensing margin and latency, are simulated with a voltage-mode sense amplifier for different array sizes and nonlinearity of the selector devices. Finally, state-of-the-art performance and mechanism of selector devices are summarized and they are classified as Type I selector with exponential current–voltage (I–V) characteristics and Type II selector with threshold I–V characteristics. Design challenges and device engineering guidelines are discussed for both types of selector in the summary.     

A low leakage TG-CNTFET–based inexact full adder for low power image processing applications

This paper presents a highly stable, low leakage inexact full adder (FA) which is based on top gate carbon nanotube field effect transistors (TG-CNTFET) for motion detector applications. Inexact arithmetic circuits are highly accepted in low power multimedia applications. Circuit level metrics, ie, average power, propagation delay, power-delay product (PDP), and leakage power dissipation as well as application level metric such as peak signal to noise ratio (PSNR) are considered to compare the performance of proposed inexact FA. All the simulations are performed using HSPICE tool with Stanford 32-nm TG-CNTFET model. The operating frequency used for simulation is 1-Ghz with 0.9-V supply voltage. Proposed inexact FA successfully achieve manifold reduction in leakage power as well as consume 89.2% lesser energy as compared with latest existing inexact FA while having other parameters in acceptable range. Simulations using MATLAB show satisfactory image quality and PSNR value for motion detection applications. The effect of variations in voltage and temperature on leakage power is also presented which confirms stability of the proposed circuit.     

Design of a contention‐free parallel double‐flow MAP decoder

Parallel processing and double‐flow methods, which are used to increase the speed of turbo‐code decoding, cause memory contentions. Although memory contentions due to parallel processing can be resolved by adopting the quadratic polynomial permutation (QPP) interleaver, the double‐flow method still causes memory contentions because of its read/write sequences from both ends of the input packets. Thus, we propose a modified architecture to resolve memory contentions for the double‐flow method to fit the QPP interleaver. In our experiment, the proposed method has a shorter decoding time and smaller hardware size compared the conventional method. A bit‐accurate simulation was performed, and hardware implementation with field‐programmable gate arrays (FPGAs) led to a high throughput of 80 Mbps. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.